Memory Controller Dynamic Strobe Point Detection
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Solution Overview
Problem
Existing memory controllers face challenges in ascertaining the strobe point for data during normal operation, leading to potential misalignment and increased power consumption due to varying operating conditions, especially in systems without phase adjusters.
Innovation Solution
A memory controller with a timing adjustment part that includes data skew and strobe adjustment mechanisms, along with detection and calculation components to determine dynamic timing information for each data signal, allowing for real-time strobe point detection and adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If calibration is performed in a special operation mode to set delay values, then timing alignment between data signal and strobe point is improved, but the ability to ascertain timing margin during normal operation is lost
Solution Approach 1:
The patent applies preliminary action by performing calibration in a special operation mode before normal operation to set optimal delay values for timing alignment. The calibration process pre-adjusts the variable delay circuit and fixed delay circuit to ensure proper strobe point alignment, and this preset configuration is then used during normal operation without requiring repeated calibration.
Solution Approach 2:
The patent introduces an intermediary mechanism by adding a detection circuit that monitors the timing relationship between data signals and strobe points during normal operation. This detection circuit acts as a mediator that provides timing margin information without disrupting the normal data operation, allowing verification of the calibration results while maintaining system functionality.
2Measurement precision
If multiple data signal lines simultaneously vary to reflect actual data content, then data accuracy is improved, but current consumption and transition time increase causing phase shift
Solution Approach 1:
The patent applies dynamics by making the delay circuits adjustable during operation. The variable delay circuit can dynamically adjust its delay value based on the actual data pattern being transmitted. When multiple data lines simultaneously vary causing excessive current consumption and phase shift, the system can adjust the delay to compensate and maintain proper timing alignment, optimizing performance for different data patterns.
3Loss of energy
If memory chip dispenses with phase adjuster to minimize power consumption and costs, then power consumption and cost are reduced, but ability to adjust phase difference between clock signals is lost
Solution Approach 1:
The patent merges the phase adjustment functionality into the memory controller by integrating a variable delay circuit and fixed delay circuit within the controller architecture. This consolidation allows the memory controller to compensate for phase differences between its clock signal and the memory chip's clock signal without requiring a separate phase adjuster in the memory chip, thereby maintaining phase alignment capability while reducing overall system cost and power consumption.
Data Source
AI summary
There is provided a technique that makes it possible to ascertain a strobe point for data while a memory is in operation with actual data. A memory controller 1 includes a data skew adjustment part 2 that adjusts a data skew of a read data signal, a strobe adjustment part 3 that adjusts a strobe point, a data change point detection part 4 that detects a data change point, a strobe point detection part 5 that detects a strobe point, a dynamic timing calculation part 6 that calculates dynamic timing information for each read data signal, a dynamic timing information storage part 7 that stores the dynamic timing information, and a dynamic timing information output part 8 that outputs the dynamic timing information.