Memory Controller Data Strobe Phase Synchronization

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Solution Overview

Problem

Existing memory systems face challenges in synchronizing the sampling point of a data strobe signal with the center of a time cycle of an internal data strobe signal, leading to inefficiencies in data transfer and prolonged training operations due to initial delay signal settings and external factors.

Innovation Solution

A memory system with a controller that generates a data strobe signal synchronized with an internal data strobe signal, utilizing a trainer to adjust the phase difference by inverting and delaying the signal until verification operations are successful, thereby positioning the sampling point at the center of the cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the sampling point of the data strobe signal is not synchronized with the center of the time cycle of the internal data strobe signal, then the training operation can be completed quickly with simple initial settings, but data read errors increase and data transfer efficiency decreases

Engineering Contradiction:
Improvedata read accuracyVSAvoiddata transfer efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by performing a training operation before normal data transfer. During this training phase, the controller adjusts the phase of the data strobe signal and modifies delay signals in advance to synchronize the sampling point with the center of the time cycle. This preliminary synchronization ensures high data read accuracy during subsequent operations without compromising transfer efficiency.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the phase of the data strobe signal is not adjusted during training operations, then the system operation is simpler, but the sampling point cannot be synchronized with the center of the time cycle, leading to increased data read errors

Engineering Contradiction:
Improvedata read accuracyVSAvoidsignal adjustment complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback through a verification operation that checks whether data read during the training operation matches expected values. Based on this feedback, the controller determines whether phase adjustment is needed and modifies the data strobe signal phase and delay signals accordingly. This feedback mechanism ensures high data read accuracy while automating the adjustment process to manage complexity.

Inventive Principle:
Principle #23Feedback

3Productivity

If delay signals are not modified during training operations, then the system operation is simpler, but the sampling point cannot be positioned at the center of the cycle, resulting in prolonged training operations and reduced data transfer efficiency

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoiddelay signal adjustment complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by modifying delay signals during the training operation to position the sampling point at the center of the cycle before normal operations begin. The controller adjusts these delay signals in advance based on verification results, ensuring optimal data transfer efficiency is achieved from the start of normal operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamics by making the delay signals adjustable and modifiable during the training operation. The controller dynamically changes the delay signal values based on feedback from verification operations, allowing the system to adapt and optimize the sampling point position for maximum data transfer efficiency.

Inventive Principle:
Principle #15Dynamics

4Productivity

If the sampling point is not synchronized with the center of the time cycle, then the initial delay signal settings can be simpler, but the training operation takes longer to complete and data transfer efficiency is reduced

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidtraining operation duration
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by completing the sampling point synchronization during the training operation before normal data transfer begins. The controller performs phase adjustments and delay signal modifications in advance to ensure the sampling point is positioned at the center of the time cycle, thereby optimizing data transfer efficiency for all subsequent operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10867648B2Memory system and operating method thereof
Publication Date: 2020.12.15 SK HYNIX INC
  • US10867648B2 patent drawing
  • US10867648B2 patent drawing
  • US10867648B2 patent drawing

AI summary

A memory system includes a memory and a controller for providing the memory with a data strobe signal; and data synchronized with an internal data strobe signal, wherein the controller includes a signal generator for generating the data strobe signal, an inverter for selectively outputting one between a non-inverted data strobe signal having the same phase as the data strobe signal and an inverted data strobe signal having an inverted phase to the phase of the data strobe signal based on an inversion signal, a delayer for delaying the inverted data strobe signal or the non-inverted data strobe signal based on a delay signal and outputting the internal data strobe signal, and a trainer for performing a verification operation on the synchronized data and generating the inversion signal and the delay signal based on the verification operation result.