Memory Controller Sub-Arbiter Segmentation for DDR4 Scheduling
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Solution Overview
Problem
Memory controllers face difficulties in operating at fast enough speeds to efficiently schedule memory accesses in modern high-speed memory systems, such as DDR4, due to the complexity of scanning and picking requests from deep queues while maximizing bus bandwidth.
Innovation Solution
A memory controller architecture that includes a command queue and a plurality of sub-arbiters to select sub-arbitration winners among memory access requests, with a final arbiter to prioritize and issue memory commands, allowing for efficient scheduling and utilization of memory bus bandwidth by distinguishing between page hits, conflicts, and misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single arbitration mechanism is used to select memory access requests from the command queue, then the device complexity is low, but the productivity is insufficient to keep up with high-speed memory interfaces like DDR4
Solution Approach 1:
The arbiter is divided into multiple parallel sub-arbiters (first sub-arbiter, second sub-arbiter, third sub-arbiter), each handling different types of memory access requests (page hits, page conflicts, page misses). This segmentation allows simultaneous processing of different request types, increasing scheduling throughput to match high-speed memory interfaces while keeping each individual sub-arbiter relatively simple.
2Productivity
If the memory controller operates at lower speeds, then the device complexity is manageable, but it cannot efficiently utilize the bus bandwidth of modern high-speed memory technologies
Solution Approach 1:
By segmenting the arbitration function into parallel sub-arbiters that can independently evaluate different types of memory requests simultaneously, the controller achieves high scheduling throughput without requiring the entire controller to operate at extremely high speeds. This enables efficient utilization of DDR4 bus bandwidth while maintaining manageable controller complexity.
3Productivity
If parallel sub-arbiters are implemented to increase scheduling throughput, then the productivity improves, but the device complexity increases
Solution Approach 1:
The arbitration function is segmented into specialized sub-arbiters handling specific request types (page hits, conflicts, misses), allowing parallel processing and high throughput.
Solution Approach 2:
Instead of having a single complex arbiter try to handle all request types sequentially, the patent inverts the approach by using multiple simple specialized sub-arbiters working in parallel, with a final arbiter selecting among their results. This inversion simplifies individual components while achieving high overall throughput.
Data Source
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AI summary
In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.