Memory Controller Wear Leveling via Super Block Erase State Count
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Solution Overview
Problem
Existing memory systems face challenges in extending the lifespan of memory devices due to uneven wear distribution across memory dies, leading to premature degradation when data is intensively stored on specific memory dies.
Innovation Solution
A memory system and operating method that distribute data by identifying memory dies with the smallest and largest number of super blocks in an erase state, moving data from the first to the second to balance the erase state count, thereby preventing excessive wear on individual memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored on memory dies without wear leveling, then storage capacity is utilized, but uneven wear distribution causes premature degradation of specific memory dies
Solution Approach 1:
The patent changes the parameter of data distribution by monitoring the number of super blocks in erase state across different memory dies and dynamically adjusting where data is stored. This ensures uniform wear distribution and extends memory system lifespan while maintaining storage efficiency
Solution Approach 2:
The memory controller implements a feedback mechanism by continuously monitoring the erase state count of super blocks on each memory die and using this information to make intelligent decisions about data placement, thereby preventing premature degradation of specific dies
2Productivity
If data is intensively stored on specific memory dies, then short-term storage performance is achieved, but wear on those dies increases leading to premature degradation
Solution Approach 1:
The system dynamically changes the storage parameter by selecting target memory dies based on their current super block erase state count, ensuring that data is always stored on dies with the most available erase blocks. This balances wear distribution while maintaining high storage performance
Data Source
AI summary
Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. In one aspect, a memory system is provided to comprise a memory device including a plurality of memory dies, each memory die including a plurality of memory blocks for storing data and different groups of memory blocks form one or more super blocks; and a memory controller in communication with the memory device and configured to count the number of super blocks in an erase state included in each memory die to identify a first memory die having the smallest number of super blocks in the erase state and a second memory die having the largest number of super blocks in the erase state, and move data stored in a first super block included in the first memory die to a second super block included in the second memory die.