Memory Controller Suspend-Resume Logic for Flash Read Latency
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Solution Overview
Problem
In Flash memory systems, long execution times for erasure and programming commands lead to delays for other commands, such as read commands, which existing techniques have not adequately addressed, resulting in inefficiencies and increased latency.
Innovation Solution
A method where a memory controller assesses the progress of ongoing erasure or programming commands to decide whether to suspend, abort, or complete them to execute read commands efficiently, using progress indications to minimize latency and overhead, thereby optimizing read command performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device executes erasure or programming commands with long execution time, then the memory can complete data storage operations, but other commands such as read commands suffer long delays
Solution Approach 1:
The patent implements dynamic suspension and resumption of erasure/programming commands based on real-time progress monitoring. The memory controller continuously monitors the execution progress of long-duration commands and dynamically decides whether to suspend them to allow read commands to execute, thereby optimizing the timing balance between completing storage operations and reducing read latency
Solution Approach 2:
The patent employs feedback mechanisms where the memory controller receives progress indications from the memory device during command execution. This feedback loop enables the controller to adjust command execution strategies by monitoring actual progress and making informed decisions about suspension/resumption to minimize overall system latency
2Loss of time
If the memory controller suspends erasure or programming commands to execute read commands, then read command latency is reduced, but the erasure or programming operations are delayed
Solution Approach 1:
The system dynamically adjusts command execution by suspending long-duration erasure/programming operations only when necessary to allow read commands to proceed. The decision to suspend or complete is based on real-time progress monitoring, ensuring that suspension occurs only when it optimizes overall system performance rather than arbitrarily delaying storage operations
Solution Approach 2:
The patent changes the execution state parameter of erasure/programming commands between active and suspended based on monitored progress. The memory controller adjusts the operational parameters of these commands dynamically, transitioning them between completion mode and suspension mode to optimize the balance between read latency reduction and storage operation completion
3Productivity
If the memory controller continuously monitors command progress to make suspension decisions, then read command performance is optimized, but device complexity increases
Solution Approach 1:
The patent uses feedback mechanisms where the memory controller receives progress indications from the memory device during command execution. This feedback loop enables the controller to adjust command execution strategies by monitoring actual progress and making informed decisions about suspension/resumption to minimize overall system latency
Solution Approach 2:
The memory device provides progress indications autonomously during command execution, enabling the controller to make suspension decisions without requiring complex external monitoring systems. The device essentially services its own progress tracking, reducing the complexity burden on the controller
Data Source
AI summary
A method includes executing a first memory access operation in a memory. A progress indication, which is indicative of a progress of execution of the first memory access operation, is obtained from the memory. Based on the progress indication, a decision is made whether to suspend the execution of the first memory access operation in order to execute a second memory access operation.