Memory Controller Suspend Resume for 3D Flash Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
3D flash memory technologies experience longer program times due to one-shot programming, causing bottlenecks in busy die and latency issues for higher priority operations like read operations during mixed read/write workloads.
Innovation Solution
A memory controller is implemented to detect and suspend lower priority memory access operations, allowing higher priority operations to execute first, and resume the suspended operations when no higher priority operations are available, thereby managing memory access efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one-shot programming is used to program multiple memory pages in a single operation, then programming efficiency is improved, but program time increases significantly causing bottlenecks on busy die
Solution Approach 1:
The patent implements dynamic suspension and resumption of programming operations based on real-time workload conditions. The memory controller monitors incoming operations and dynamically suspends ongoing one-shot programming operations when higher-priority operations arrive, then resumes them when the queue is clear. This dynamic adjustment resolves the contradiction by making the programming process adaptable to varying workload conditions rather than static.
Solution Approach 2:
The patent changes the execution state parameter of programming operations from continuous to suspended/resumed. By introducing suspend and resume commands that modify the execution parameter of ongoing programming operations, the system can prioritize different operation types dynamically. This parameter change allows the system to maintain high programming efficiency while reducing latency for time-sensitive operations.
2Productivity
If long program operations are executed continuously, then programming throughput is improved, but latency for higher priority operations such as read operations increases
Solution Approach 1:
The patent performs preliminary detection of higher-priority operations before allowing long program operations to complete. The memory controller continuously monitors the operation queue and detects incoming read operations that require low latency. When such operations are detected, the controller preemptively suspends the ongoing programming operation, ensuring that read operations can execute without excessive latency while still allowing programming operations to make progress through resumption.
3Productivity
If multiple memory pages are programmed simultaneously in one-shot programming, then programming efficiency is improved, but the bottleneck on busy die worsens
Solution Approach 1:
The patent introduces dynamic control through suspend and resume operations that adjust the execution flow based on real-time die conditions. When the die becomes congested with multiple simultaneous operations, the controller can suspend less critical programming operations to reduce the operational complexity on the die. This dynamic adjustment reduces the effective device complexity during high-load periods while maintaining overall programming efficiency through resumption of suspended operations.
Data Source
AI summary
A memory controller manages memory access operations through a flash memory interface of a memory array of a solid-state storage device connected to a host. The memory controller executes a first memory access operation in the memory array. The first memory access operation has a first priority. The memory controller detects a suspending memory access operation available for execution in the memory array and having a higher priority than the first priority. The detection operation distinguishes between suspending memory access operations and non-suspending memory access operations. The memory controller suspends execution of the first memory access operation in the memory array and executes one or more memory access operations having higher priorities than the first priority and being available for execution in the memory array. The memory controller resumes the execution of the first memory access operation in the memory array.