Memory Controller Suspend Timing for NAND Flash
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Solution Overview
Problem
In NAND-type flash memory systems, the existing suspend operations can lead to inefficiencies and increased latency due to improper timing of suspend commands during erase and write operations, which can result in wasted processing time and potential chip deterioration.
Innovation Solution
The memory system employs a timer-based mechanism where the NAND controller starts a timer upon initiating an operation, prohibits suspend commands until a threshold is reached, and updates the threshold based on the operation's status, allowing for more efficient suspend and resume operations to minimize downtime and maintain chip integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If suspend commands are issued immediately during erase/write operations, then read operation latency is reduced, but operation execution efficiency deteriorates and chip reliability decreases
Solution Approach 1:
The controller performs preliminary actions by acquiring the status of the erase/write operation before issuing a suspend command. It determines whether to suspend based on the operation's execution status (e.g., whether the operation is in a state where suspension is safe), thereby preventing premature or inappropriate suspension that would harm chip reliability while still enabling timely read operations.
2Reliability
If suspend commands are prohibited during erase/write operations, then chip reliability is maintained, but read operation latency increases
Solution Approach 1:
The controller continuously monitors the execution status of erase/write operations through status acquisition. Based on this feedback, the controller dynamically decides whether to permit or prohibit suspend commands. This feedback mechanism ensures that suspend operations are only allowed when they will not compromise chip reliability, thereby maintaining reliability while minimizing read operation latency.
3Speed
If suspend operations are performed without status checking, then processing speed increases, but execution efficiency decreases due to wasted processing time
Solution Approach 1:
The patent replaces mechanical/status-based control with a timer-based control mechanism. The controller uses a timer to track the execution time of erase/write operations and automatically determines the appropriate moment to suspend, eliminating the need for continuous status checking while maintaining execution efficiency. This substitution speeds up the suspend operation process while avoiding wasted processing time.
Data Source
AI summary
According to an embodiment, a memory system including: a semiconductor memory configured to store data, a memory controller configured to issue a first command to suspend a first operation to the semiconductor memory which is executing the first operation, wherein the memory controller is configured to prohibit the issuance of the first command until a time in which the first operation is executed passes a first threshold, acquire a status of the semiconductor memory which is executing the first operation, and update the first threshold to a second threshold in accordance with the status.