Memory Controller Switching Modes to Prevent Read Disturbance
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Solution Overview
Problem
In semiconductor memory devices, read disturbance causes unintended charge storage in word lines, leading to reading defects and hardware errors due to the shifting of threshold voltages in memory cells connected to non-selected word lines, resulting in performance degradation.
Innovation Solution
A memory controller and system that switch operation modes from high bit to low bit based on read disturbance influence, reducing the number of bits written to memory cells and increasing the distance between threshold voltage distributions to prevent overlapping and errors, using a mode management table to track read operations and switch modes accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reading is performed in high bit mode to maximize data capacity, then productivity is improved, but reliability deteriorates due to read disturbance causing threshold voltage shifting and hardware errors
Solution Approach 1:
The patent dynamically switches between high bit mode and low bit mode based on the read disturbance level detected in the memory block. When read disturbance exceeds a threshold, the system transitions from high bit mode (higher productivity, lower reliability) to low bit mode (lower productivity, higher reliability), thereby adapting the reading strategy to current memory conditions to maintain overall system reliability while maximizing productivity when safe
Solution Approach 2:
The patent changes the reading parameter (bit mode) based on the state of the memory block. By detecting threshold voltage shifts caused by read disturbance and switching between different reading modes (high bit mode with more bits per cell, low bit mode with fewer bits per cell), the system adjusts the reliability-productivity tradeoff dynamically according to actual memory conditions
2Productivity
If the number of bits written to memory cells is increased to improve storage capacity, then productivity is improved, but manufacturing precision requirements increase due to closer threshold voltage distributions
Solution Approach 1:
The system dynamically adjusts the number of bits written to memory cells based on the detected read disturbance level. In high bit mode, more bits are stored per cell (higher capacity, tighter voltage margins). When read disturbance is detected, the system switches to low bit mode, writing fewer bits per cell (lower capacity, wider voltage margins), thereby adapting to manufacturing variations and read disturbance conditions
Solution Approach 2:
The patent changes the writing parameter (number of bits per cell) based on memory block conditions. By switching between high bit mode (higher capacity, requires tighter precision) and low bit mode (lower capacity, more tolerant of precision variations), the system optimizes the balance between storage capacity and manufacturing precision requirements
Data Source
AI summary
A memory controller includes a memory interface that is connected to a non-volatile memory that includes a plurality of memory cells, and a control unit. The control unit controls the memory interface to perform writing of data that has a first number of bits to a first memory cell in an n-bit write mode (where n is 2 or more), and when performing reading of the data written into the first memory cell, to control the memory interface to perform reading of data in an m-bit read mode (where m is less than n), as a result of which data that has a second number of bits which is smaller than the first number of bits, is returned from the first memory cell.