Programmable Memory Controller Switching for HBM Routing Congestion
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Solution Overview
Problem
High-speed memory systems like HBM face routing congestion and increased latency due to high data transfer demands, leading to reduced performance and increased power consumption in FPGA applications.
Innovation Solution
Implementing programmable switch circuits that cascade multiple channel circuits to operate as a 1-to-N or N-to-N memory controller system, reducing routing resources and improving signal integrity and thermal distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-speed memory systems are implemented to increase bandwidth, then data transfer speed is improved, but routing congestion and latency increase
Solution Approach 1:
The memory controller is divided into multiple independent channel circuits (first channel circuit, second channel circuit, etc.), each capable of handling data transfers to different memory circuits. This segmentation distributes the routing load across multiple paths, reducing congestion in any single routing path while maintaining high data transfer speeds.
Solution Approach 2:
The patent introduces a programmable switch circuit layer that adds a dimensional layer of control between the memory controller and memory circuits. This switch circuit layer enables dynamic routing decisions, allowing data to be directed through optimal paths in the routing dimension, thereby reducing congestion and latency while maintaining high transfer speeds.
2Productivity
If more routing wires are added to handle high bandwidth demands, then data transfer capacity is improved, but signal integrity and thermal distribution deteriorate
Solution Approach 1:
By segmenting the data transfer paths into multiple channel circuits with dedicated routing wires, the patent reduces the total number of wires needed compared to a single high-bandwidth path. Each channel circuit handles a portion of the bandwidth, distributing the signal load and reducing congestion-related signal integrity issues.
Solution Approach 2:
The programmable switch circuit acts as an intermediary between the memory controller and memory circuits, managing signal routing dynamically. This intermediary layer optimizes signal paths, reducing interference and maintaining signal integrity while achieving high bandwidth utilization through efficient resource sharing.
3Ease of operation
If traditional memory controller configuration is used, then data access is simplified, but routing resource duplication and congestion occur
Solution Approach 1:
The programmable switch circuit provides multi-functional routing capabilities, serving multiple channel circuits and memory circuits through a shared resource. This universal switch fabric eliminates the need for dedicated routing resources for each channel, reducing overall routing resource duplication while maintaining simple data access through programmed routing configurations.
Solution Approach 2:
The patent merges multiple routing resources into a unified programmable switch fabric that serves all channel circuits. By combining previously separate routing paths into a shared, dynamically controllable structure, the system reduces total routing resources needed while maintaining ease of operation through centralized control.
Data Source
AI summary
A memory controller circuit includes a first channel circuit having a first programmable switch circuit that is programmable to provide a first request signal indicating a first data access request to a memory circuit. The first programmable switch circuit is programmable to provide a first write data signal indicating first data for storage in the memory circuit. The memory controller circuit includes a second channel circuit having a second programmable switch circuit that is programmable to provide one of the first request signal received from the first programmable switch circuit or a second request signal indicating a second data access request to the memory circuit. The second programmable switch circuit is programmable to provide one of the first write data signal received from the first programmable switch circuit or a second write data signal indicating second data for storage in the memory circuit.