Memory Controller Read-Write Switching Point Scheduling
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Solution Overview
Problem
The performance of memory systems is affected by the method of scheduling commands for volatile semiconductor memory devices, leading to inefficiencies in data input/output operations.
Innovation Solution
A memory system that separates read requests and write requests using a read-write switching point, blocks unnecessary bank requests before this point, and schedules bank requests for the next turn after the switching point, optimizing the scheduling of commands to improve performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory controller schedules bank requests without separation between read and write operations, then the scheduling process is simple, but the memory system performance deteriorates due to increased latency and inefficient I/O operations
Solution Approach 1:
The patent divides the scheduling process into two distinct phases: a first turn for processing read requests and a second turn for processing write requests. This segmentation allows the memory controller to handle read and write operations separately, reducing conflicts and improving overall memory system performance by optimizing the timing and sequence of bank requests.
Solution Approach 2:
The patent introduces a preliminary action by setting a near switching point before the actual read-write switching point. This allows the memory controller to proactively manage the transition between read and write turns, blocking unnecessary bank requests in advance and preparing the scheduling structure before the switching occurs, thereby improving performance without excessive complexity.
2Loss of energy
If the memory controller processes all I/O requests in a single turn without blocking, then the processing is continuous, but power consumption increases due to unnecessary bank requests being scheduled
Solution Approach 1:
The patent applies preliminary anti-action by blocking unnecessary bank requests between the near switching point and the read-write switching point. This preventive blocking stops unwanted operations before they can consume power, while still allowing essential I/O requests to proceed, thus reducing power loss without significantly impacting processing efficiency.
3Loss of time
If the memory controller allows all bank requests to be scheduled without restriction, then the scheduling is flexible, but latency increases due to unnecessary state switching operations
Solution Approach 1:
The patent segments the scheduling process into distinct turns for reads and writes, with controlled flexibility within each segment. This allows the system to maintain adaptability for handling different I/O request patterns while reducing latency by preventing unnecessary bank state switching operations that would occur in an entirely unrestricted scheduling approach.
Data Source
AI summary
A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.