Memory Controller Read-Retry Logic Using Syndrome-Weight Analysis

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Solution Overview

Problem

Existing memory systems face challenges in reading data with a large number of error bits due to changes in threshold voltage distributions of memory cells, leading to ineffective error correction decoding.

Innovation Solution

A memory controller with an error correction circuit that performs read retry operations, stores decoding history information, and determines an optimally estimated read voltage based on syndrome weights to minimize error bits, using both hard and soft decision decoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read retry operations are performed multiple times with different read voltages, then the number of error bits in read data is reduced, but the reading time increases

Engineering Contradiction:
Improvenumber of error bitsVSAvoidreading time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs read retry operations in advance with different read voltages and stores the results in a buffer memory. When the same data is accessed again, the previously obtained decoded data can be directly used without repeating the read retry process, thereby reducing the time loss while maintaining low error bit counts.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the read voltage parameter across multiple read retry operations (first read voltage, second read voltage, etc.) to optimize the number of error bits. By systematically varying the voltage parameter and storing the results, the system finds optimal read conditions without repeatedly performing full read retry sequences.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the number of read retry operations is increased, then error correction decoding efficiency is improved, but the processing complexity increases

Engineering Contradiction:
Improveerror correction decoding efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system segments the read retry process into multiple independent operations with different read voltages. Each read retry operation is handled separately and its result is stored in the buffer memory. This segmentation allows the system to manage complexity by treating each voltage level as an independent trial rather than a monolithic complex process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The buffer memory acts as an intermediary that stores both the read data and the corresponding decoded data from multiple read retry operations. This intermediary component manages the complexity by organizing results from different voltage levels and making them accessible for future operations without requiring the system to reprocess the same data repeatedly.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If read retry operations are performed with different read voltages, then data reading reliability is improved, but the energy consumption increases

Engineering Contradiction:
Improvedata reading reliabilityVSAvoidenergy consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system performs energy-consuming read retry operations with different voltages in advance and stores the results. When the same data needs to be read again, the system can use the pre-obtained decoded data from the buffer memory without repeating the energy-intensive read retry process, thereby reducing overall energy consumption while maintaining high reading reliability.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12436838B2Memory controller and memory system including the same
Publication Date: 2025.10.07 SK HYNIX INC
  • US12436838B2 patent drawing
  • US12436838B2 patent drawing
  • US12436838B2 patent drawing

AI summary

Provided herein may be a memory controller and a memory system including the same. The memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.