Memory Controller Unaligned Access Tagged Buffer
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Solution Overview
Problem
In systems with a single bank memory architecture, unaligned memory access requires multiple memory access operations, leading to increased latency and inefficiency, while multi-port and multi-bank architectures struggle to leverage their full potential due to port limitations.
Innovation Solution
A computing apparatus with a memory controller that includes a memory access manager and a tagged buffer, allowing data to be stored in aligned word units and extracted for unaligned memory access by using multiple data buffers and a tag multiplexor to combine requested bytes, enabling efficient unaligned memory access with reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bank memory architecture is used, then device complexity is reduced, but unaligned memory access requires multiple memory access operations increasing latency and reducing productivity
Solution Approach 1:
The memory system is segmented into multiple banks (first bank, second bank, etc.), each capable of independent access. This segmentation allows simultaneous access to different memory banks, enabling unaligned memory access to be completed in a single operation rather than requiring multiple sequential accesses, thus improving productivity without significantly increasing overall system complexity
Solution Approach 2:
A memory controller is introduced as an intermediary component that manages access to multiple memory banks. The controller receives unaligned memory access requests, determines which banks are involved, and coordinates simultaneous access to the required banks, thereby enabling efficient unaligned access while abstracting the complexity from the processor
2Loss of time
If a multi-port and multi-bank memory architecture is used, then unaligned memory access latency is reduced, but port availability decreases when one port accesses multiple banks
Solution Approach 1:
The memory banks are segmented and assigned to specific ports (first port controls first and second banks, second port controls third and fourth banks). This segmentation ensures that when one port accesses its assigned banks, other ports remain available to access their own banks, preventing port starvation and maintaining system versatility
Solution Approach 2:
The memory controller is configured to predict when unaligned memory access may be required and proactively loads data from multiple banks into buffers in advance. This preliminary action ensures that when an unaligned access request arrives, the data is already available in the buffers, reducing latency without requiring additional port usage at the moment of access
Data Source
AI summary
A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer.