Memory Controller Target Refresh Address Generation
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Solution Overview
Problem
Conventional memory systems face inefficiencies in target refresh operations due to the lack of internal evaluation and repair mechanisms for target address generation, leading to reduced accuracy and increased burden on memory devices.
Innovation Solution
A memory system with a memory controller that includes a built-in self-test (BIST) circuit and built-in redundancy analysis (BIRA) circuit to collaboratively generate target addresses with the memory device, perform test operations, and execute repair operations based on test results, thereby enhancing refresh efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If only the memory device generates target addresses, then the memory device bears the full burden of target refresh operations, but the system lacks internal evaluation and repair mechanisms reducing accuracy
Solution Approach 1:
The target address generation function is segmented between the memory controller and memory device. The memory controller generates a first target address based on activation history, while the memory device generates a second target address through random sampling. This division reduces the burden on the memory device and improves accuracy through collaborative generation.
Solution Approach 2:
A feedback mechanism is introduced where the memory controller performs BIST and BIRA operations to evaluate the generated target addresses. Test data is written, read back, and compared to detect errors. Repair control signals are generated based on comparison results to correct faulty addresses, creating a closed-loop feedback system that continuously improves reliability.
2Measurement precision
If the memory controller and memory device collaboratively generate target addresses, then the accuracy of target refresh is improved, but the system complexity increases due to additional test and repair mechanisms
Solution Approach 1:
The memory controller performs self-diagnosis and self-repair through built-in test modules and built-in redundancy analysis circuits. The system uses its own resources to evaluate and correct target address generation errors without requiring external intervention, maintaining improved accuracy while managing complexity through integrated self-service functions.
3Reliability
If BIST and BIRA circuits are added to the memory controller, then internal evaluation and repair capabilities are enabled, but the device complexity increases
Solution Approach 1:
The BIST and BIRA circuits are merged into the memory controller to create an integrated test and repair system. This consolidation enables internal evaluation and repair capabilities while managing complexity through unified design, allowing the memory controller to perform self-diagnosis and self-repair functions without requiring separate external systems.
Data Source
AI summary
A memory controller includes: a test module for generating a test command, a test address, and test data during a test operation; a refresh control module for receiving the test command and the test address as an active command and an active address, and generating a first target address by sampling the active address according to the active command, during the test operation; a command/address generation module for providing the active address together with the active command, and providing the first target refresh command together with the first target address to a memory device, while determining whether to repair the active address according to a repair control signal; and a repair analysis module for generating the repair control signal based on a comparison result of the test data and read data from the memory device, during the test operation.