Memory Controller Temperature Compensation for DRAM Timing

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Solution Overview

Problem

Dynamic random access memory (DRAM) performance is degraded due to increased write recovery time at lower temperatures, leading to higher bit error rates and reduced memory bandwidth, making it challenging to maintain optimal timing parameters across varying temperatures.

Innovation Solution

An information handling system that includes a processor and a memory system configured to determine the temperature and initiate remedial actions to maintain the temperature above a minimum threshold, using self-heating systems and temperature sensors to optimize timing parameters and prevent performance degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If write recovery parameter is increased to reduce bit error rate, then reliability is improved, but memory bandwidth deteriorates

Engineering Contradiction:
Improvebit error rateVSAvoidmemory bandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements dynamic adjustment of write recovery timing parameters based on real-time temperature sensing. The memory controller monitors temperature and adjusts timing parameters dynamically, allowing optimal performance across varying thermal conditions without sacrificing reliability or bandwidth permanently.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes timing parameters as a function of operating temperature. At different temperature ranges, different write recovery parameter values are applied, optimizing both reliability and bandwidth for each thermal condition rather than using a fixed conservative value.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If write recovery parameter is increased to ensure full charge, then reliability is improved, but write latency increases

Engineering Contradiction:
Improvewrite failure rateVSAvoidwrite latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements dynamic adjustment of write recovery timing parameters based on real-time temperature sensing. The memory controller monitors temperature and adjusts timing parameters dynamically, allowing optimal performance across varying thermal conditions without sacrificing reliability or bandwidth permanently.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes timing parameters as a function of operating temperature. At different temperature ranges, different write recovery parameter values are applied, optimizing both reliability and bandwidth for each thermal condition rather than using a fixed conservative value.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If temperature-based timing parameters are implemented, then performance at high temperature is improved, but write latency triples at low temperature

Engineering Contradiction:
Improvememory performanceVSAvoidwrite latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Instead of reducing timing parameters at low temperature (which would cause write failures), the patent inverts the approach by using temperature-compensated timing that maintains appropriate margins across all temperatures. The system adjusts timing based on temperature in a way that prevents both write failures and excessive latency variation.

Inventive Principle:
Principle #13The other way round (Inversion)

Solution Approach 2:

The system changes timing parameters as a function of operating temperature. At different temperature ranges, different write recovery parameter values are applied, optimizing both reliability and bandwidth for each thermal condition rather than using a fixed conservative value.

Inventive Principle:
Principle #35Parameter changes

4Reliability

If variable memory latency is introduced for temperature compensation, then reliability is improved, but program performance deteriorates

Engineering Contradiction:
Improvewrite success rateVSAvoidprogram timing sensitivity
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent implements a feedback mechanism where the memory controller monitors temperature and dynamically adjusts timing parameters to maintain consistent performance. This feedback loop compensates for temperature variations automatically, preventing both write failures and timing-related program issues.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes timing parameters as a function of operating temperature. At different temperature ranges, different write recovery parameter values are applied, optimizing both reliability and bandwidth for each thermal condition rather than using a fixed conservative value.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The system effectively maintains optimal memory performance by ensuring that timing parameters remain efficient, reducing write latency and bandwidth issues associated with temperature fluctuations, thereby enhancing overall memory device performance.

Implementation Method 1

initiate one or more remedial actions to increase the temperature above the minimum threshold temperature

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Implementation Method 2

determine a temperature associated with the memory system

Methodology Applied
Scientific EffectTemperature sensing: Thermistor

Data Source

PatentUS9678490B2Systems and methods for temperature-based performance optimization of memory devices
Publication Date: 2017.06.13 DELL PROD LP
  • US9678490B2 patent drawing
  • US9678490B2 patent drawing
  • US9678490B2 patent drawing

AI summary

In accordance with embodiments of the present disclosure, a memory system may include one or more memory modules and a memory controller communicatively coupled to one or more memory modules. The memory controller may be configured to determine a temperature associated with the memory system and determine if the temperature is below a minimum threshold temperature, wherein the minimum threshold temperature is a predetermined margin greater than a critical temperature below which one or more timing parameters of the memory system are of greater durations than they are when the temperature is above the critical temperature, and further wherein the predetermined margin is zero or greater. The memory controller may also be configured to initiate one or more remedial actions to increase the temperature above the minimum threshold temperature if the temperature is below the minimum threshold temperature.