Memory Controller Tensor Address Generation
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving fast and efficient memory access patterns, particularly in multi-core processor systems where tensor processing requires repetitive and intensive memory access.
Innovation Solution
The implementation of a memory controller with a data address generator that generates sequences of memory addresses based on tensor or matrix operations, allowing for concurrent read/write operations and utilizing a data buffer for efficient data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional memory access patterns are used in multi-core processor systems, then basic memory operations can be performed, but processing speed decreases and power consumption increases due to repeated memory access for tensor operations
Solution Approach 1:
The patent applies preliminary action by pre-fetching data blocks into the memory controller buffer before they are actually needed for processing. The system predicts which data will be needed based on tensor operation patterns and loads it in advance, eliminating wait times and reducing the frequency of memory access operations, thereby improving processing speed and reducing power consumption.
Solution Approach 2:
The patent introduces a buffer within the memory controller as an intermediary between the main memory and the processing units. This buffer stores frequently accessed data blocks, allowing multiple processing cores to access the same data without requiring repeated trips to main memory. The intermediary buffer thus reduces memory access frequency, improves processing speed, and lowers power consumption.
2Productivity
If repeated memory access is performed for tensor processing operations, then complete processing can be achieved, but memory access efficiency decreases and processing time increases
Solution Approach 1:
The system performs preliminary actions by pre-loading data blocks into the memory controller buffer based on predicted access patterns. This allows the processing units to retrieve data from the fast buffer rather than waiting for slow main memory access, thereby improving memory access efficiency and reducing processing time.
Solution Approach 2:
The patent implements continuity of useful action by keeping the memory controller buffer continuously populated with data that is likely to be needed. The system maintains this buffer state across multiple operations, ensuring that processing can continue without interruption or idle waiting time, thus improving overall productivity and reducing processing time.
3Speed
If data is stored in main memory for tensor operations, then data availability is ensured, but access speed decreases due to the distance and complexity of memory access
Solution Approach 1:
The patent applies segmentation by dividing the memory hierarchy into two distinct segments: main memory for long-term storage and a buffer within the memory controller for frequent access. This segmentation allows data to be stored in main memory when not needed while keeping frequently accessed data in the faster buffer, improving access speed without requiring all data to be constantly available in fast memory.
Solution Approach 2:
The memory controller buffer serves as an intermediary that simplifies the complexity of memory access. Instead of processing units directly accessing main memory for every operation, they access the buffer which handles the complexity of data management, addressing, and coordination with main memory. This intermediary approach reduces access complexity and improves speed.
Data Source
AI summary
Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.