Memory Controller Latent Error Detection via Super Block Test Reads
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Solution Overview
Problem
Memory systems face challenges in preventing errors in memory blocks, particularly due to latent errors that can occur during program or read operations, which existing technologies do not effectively address.
Innovation Solution
A memory system architecture that divides memory blocks into super blocks, with a controller performing test read operations on remaining blocks within the same super block when an error occurs, allowing for data shifting to ensure data integrity by identifying and relocating valid data to healthy blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a program operation is performed on a selected memory block, then data is stored in the memory block, but latent errors may occur in the memory block or other blocks in the same super block
Solution Approach 1:
The patent performs a test read operation on remaining memory blocks in the same super block immediately after a program operation fails on a selected memory block. This preliminary action detects latent errors before they can cause data corruption, allowing the system to proactively identify and handle potentially affected blocks.
Solution Approach 2:
The patent implements a feedback mechanism where the result of a program operation triggers a test read operation on other blocks in the same super block. This feedback loop allows the system to continuously monitor and detect latent errors that may have been induced by the program operation, enabling real-time error management.
2Reliability
If test read operations are performed on remaining memory blocks after a program fail, then latent errors are detected, but additional time and operations are required
Solution Approach 1:
The patent performs test read operations on remaining memory blocks in the same super block as a preventive measure immediately when a program fail occurs. This preliminary anti-action detects latent errors before they can propagate and cause further data corruption, allowing the system to counteract potential errors before they become problematic.
Solution Approach 2:
Instead of testing all memory blocks in the system, the patent applies test read operations only to remaining blocks within the same super block as the failed program operation. This partial action approach focuses resources on the most likely affected areas, reducing the overall time and computational overhead while maintaining effective error detection.
3Reliability
If data shift operation is performed on memory blocks with read fails, then valid data is relocated to healthy blocks, but device complexity increases
Solution Approach 1:
The patent introduces a controller as an intermediary that manages the data shift operation between memory blocks. The controller receives test read results, identifies blocks with latent errors, and coordinates the relocation of valid data from affected blocks to healthy blocks. This intermediary simplifies the overall system architecture by centralizing error management logic.
Solution Approach 2:
The patent implements a data copying mechanism where valid data from memory blocks with latent errors is read and copied to healthy memory blocks in the same super block. This copying approach ensures data redundancy and recovery capability without requiring complex data reconstruction algorithms, simplifying the error recovery process.
Data Source
AI summary
Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device including super blocks, each of the super blocks including a plurality of memory blocks, and a controller configured to control the memory device so that a program operation is performed on a selected memory block within any one of the super blocks based on a request from a host, wherein, when a program fail occurs during the program operation that is performed on the selected memory block of the selected super block, the controller is configured to control the memory device so that a test read operation is performed on remaining memory blocks, besides the selected memory block, of the selected super block.