Memory Controller Dynamic Error Threshold Adjustment
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Solution Overview
Problem
Conventional semiconductor memory devices face data retention issues due to frequent program/erase cycles, leading to unnecessary write cycles and reduced longevity, as they apply the same periodic rewriting rate regardless of access frequency.
Innovation Solution
The memory controller dynamically adjusts error threshold values based on erase count ranges, setting higher thresholds for less frequent access and lower thresholds for higher access frequencies, triggering data refresh only when error bits exceed the adjusted threshold, thereby optimizing data retention and reducing unnecessary write cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic rewriting is applied to all memory units regardless of access frequency, then data retention is improved, but unnecessary write cycles increase and device lifetime decreases
Solution Approach 1:
The patent implements dynamic adjustment of error threshold values based on erase count ranges. The memory controller monitors the erase count of each memory unit and adjusts the error threshold dynamically: higher thresholds for low erase counts (less frequent access) and lower thresholds for high erase counts (more frequent access). This dynamic approach ensures data refresh only when necessary, avoiding unnecessary write cycles and extending device lifetime while maintaining data retention.
Solution Approach 2:
The patent changes the parameter of error threshold values based on the erase count of memory units. By mapping erase counts to different error threshold ranges, the system adapts the data refresh criteria to the actual wear level of each memory unit. This parameter change allows the system to optimize between data retention and device lifetime by being more conservative with refresh operations on heavily used memory units.
2Reliability
If data refresh is triggered frequently to prevent data loss, then data retention is improved, but write cycle consumption increases
Solution Approach 1:
The patent changes the error threshold parameter based on erase count to optimize write cycle efficiency. By setting higher error thresholds for memory units with low erase counts, the system reduces the frequency of data refresh operations. As erase count increases, the threshold decreases to maintain data retention. This adaptive parameter adjustment maximizes write cycle efficiency by triggering refresh only when actually needed.
Solution Approach 2:
The patent applies partial action by selectively refreshing only those memory units that meet the error threshold criteria rather than performing universal periodic refresh. This approach avoids excessive write cycles on memory units that do not require refresh, improving overall write cycle efficiency while maintaining adequate data retention for units that do need protection.
3Productivity
If error threshold values are kept high to reduce refresh operations, then write cycles are reduced, but data loss risk increases
Solution Approach 1:
The patent implements dynamic error threshold adjustment where the threshold value changes based on the erase count of the memory unit. High thresholds are applied to memory units with low erase counts to reduce refresh operations, while low thresholds are applied to units with high erase counts to prevent data loss. This dynamic approach balances write cycle efficiency and data retention by adapting to the actual condition of each memory unit.
Solution Approach 2:
The patent changes the error threshold parameter based on erase count ranges. By mapping different erase count ranges to different threshold values, the system optimizes the balance between reducing unnecessary refresh operations and maintaining data retention. The parameter change ensures that high thresholds (which reduce write cycles) are only applied where safe, while low thresholds (which protect against data loss) are applied to worn memory units.
Data Source
AI summary
A memory controller accesses a memory page in a memory block of a storage memory array of a memory device. The memory controller reads memory data stored in the accessed memory page. The memory controller determines a number of error bits associated with the memory data. The memory controller obtains an erase count corresponding to the accessed memory page, the erase count indicating a number of erase operations performed on the accessed memory page. The memory controller determines, from among one or more error threshold values, an error threshold value based at least on the erase count. The memory controller determines a relationship between the number of error bits and the error threshold value. The memory controller triggers a data refresh for the accessed memory block if the relationship between the number of error bits and the error threshold value satisfy a known criterion.