Memory Controller Throttling via GC Host Ratio

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Solution Overview

Problem

Current semiconductor memory systems, such as SSDs, face performance inconsistencies and inefficiencies due to garbage collection processes that affect bandwidth and consistency, particularly in high-write environments, where background garbage collection can interfere with host write commands, leading to fluctuations in the number of erased NAND flash blocks.

Innovation Solution

A semiconductor memory system and operating method that include a memory controller capable of throttling, which calculates a garbage collection (GC)/HOST ratio based on the count of invalid and valid GC blocks and adjusts throttling parameters to maintain a balance of erased blocks, thereby stabilizing performance by coordinating GC and HOST commands to share bandwidth effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If background garbage collection is performed continuously, then erased blocks are replenished, but host write commands are interfered with and performance consistency deteriorates

Engineering Contradiction:
Improveerased blocksVSAvoidperformance consistency
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

The patent implements dynamic throttling of garbage collection commands based on real-time monitoring of erased block counts and host command rates. The throttling rate is adjusted dynamically to maintain erased block counts within a target range while minimizing interference with host writes, resolving the contradiction between replenishing erased blocks and maintaining performance consistency

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system continuously monitors the number of erased blocks and host write command rates, using this feedback to adjust the garbage collection throttling rate. When erased block counts fall below the target range or host write rates increase, the throttling rate is increased to prioritize host performance, and vice versa, achieving balanced resource allocation

Inventive Principle:
Principle #23Feedback

2Productivity

If garbage collection throttling is applied, then host write performance is improved, but erased block levels may become unbalanced

Engineering Contradiction:
Improvehost write performanceVSAvoiderased blocks
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system uses feedback control by continuously monitoring erased block counts and adjusting the garbage collection throttling rate accordingly. When erased block counts fall below the target range, the throttling rate is reduced to allow more aggressive garbage collection, ensuring erased block levels are maintained while minimizing impact on host performance

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If aggressive garbage collection is performed, then erased blocks are replenished quickly, but bandwidth is consumed and host performance fluctuates

Engineering Contradiction:
Improveerased blocksVSAvoidhost write throughput
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent implements dynamic adjustment of garbage collection aggressiveness based on host workload conditions. During high host write periods, garbage collection is throttled to preserve bandwidth for host operations. During low host activity periods, garbage collection intensity is increased to replenish erased blocks, achieving balanced resource allocation without significant performance fluctuations

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10248327B2Throttling for a memory system using a GC/HOST ratio and operating method thereof
Publication Date: 2019.04.02 SK HYNIX INC
  • US10248327B2 patent drawing
  • US10248327B2 patent drawing
  • US10248327B2 patent drawing

AI summary

A semiconductor memory system and an operating method thereof include: a memory device; and a memory controller including a processor, coupled to the memory device, containing instructions executed by the processor, and configured to provide sets of throttling numbers, select a throttling mode, calculate a garbage collection (GC)/HOST ratio based on at least a part of invalid count of garbage collection (GC) blocks and valid count of BGC blocks, and adjust throttling parameters of commands in accordance with the GC/HOST ratio and a number of erased blocks.