Memory Controller Signal Routing via Through-Block Metal Routes
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Solution Overview
Problem
The existing integrated circuit (IC) layouts require significant area for signal routing between memory blocks and memory controllers, leading to increased IC size and manufacturing costs due to extensive metal routes in channels between memory blocks.
Innovation Solution
The IC layout is optimized by arranging memory blocks in rows and columns with metal routes created over the blocks, using a combination of horizontal and vertical metal layers, and buffers along these routes to reduce channel area and enhance signal routing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal routes are created in spaces between adjacent memory blocks (channels), then signal routing between memory blocks and memory controller is enabled, but area occupied by channels increases significantly
Solution Approach 1:
The patent transitions from two-dimensional routing in channel spaces to three-dimensional routing by creating metal routes that pass through the interior volumes of memory blocks. This dimensional change allows signals to be routed through the bulk material of memory blocks rather than being constrained to surface-level channel spaces, thereby reducing the area occupied by dedicated routing channels while maintaining full signal routing capability between memory blocks and the memory controller.
2Adaptability or versatility
If significant channel area is allocated for metal routes, then all memory blocks can be coupled with memory controller, but size of IC layout increases
Solution Approach 1:
The patent merges the function of dedicated routing channels with the memory block structures themselves. By creating metal routes that pass through memory blocks, the memory blocks serve dual purposes: storing data and providing internal pathways for signal routing. This consolidation eliminates the need for separate channel areas, thereby reducing overall IC layout size while maintaining the capability to couple all memory blocks with the memory controller.
Solution Approach 2:
The invention utilizes the vertical dimension by routing metal routes through the thickness of memory blocks rather than confining routing to horizontal channel spaces. This three-dimensional approach allows multiple memory blocks to share common routing pathways through the substrate, reducing the horizontal footprint required for routing and thereby decreasing overall IC layout area while preserving full connectivity.
3Reliability
If IC layout size increases due to extensive channel area, then signal routing is maintained, but manufacturing cost increases
Solution Approach 1:
The patent extracts the routing function from the channel spaces and relocates it within the memory block structures. By removing the requirement for extensive dedicated channel areas and instead utilizing the interior of memory blocks for routing, the overall IC layout size is reduced. This reduction in layout area directly translates to lower manufacturing costs, as smaller chips require less substrate material, fewer fabrication steps, and less testing time, while the signal routing functionality is preserved through the newly implemented through-block metal routes.
Data Source
AI summary
An integrated circuit (IC) layout includes various memory blocks arranged in rows and columns, and a memory controller arranged in parallel to one of the rows and the columns. The IC layout further includes metal routes that are created over the memory blocks for coupling the memory and the memory controller and facilitating signal routing therebetween. Each memory block is coupled with the memory controller by way of one or more metal routes. When the memory controller is arranged in parallel to the rows, the one or more metal routes are created over memory blocks that are included in a column, whereas when the memory controller is arranged in parallel to the columns, the one or more metal routes are created over memory blocks that are included in a row.