Memory Controller Throughput-Based Completion Signal Delay

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Solution Overview

Problem

Memory systems face inefficiencies due to frequent throttling operations, which lead to performance degradation and increased temperatures, as they often output completion signals prematurely, causing overload and necessitating throttling to prevent overheating.

Innovation Solution

A memory controller that adjusts the output of completion signals based on internal throughput, comparing current and requested throughputs to determine when to delay or send the signal, thereby reducing the frequency of throttling operations and maintaining performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the memory controller outputs completion signals promptly without considering internal throughput, then the host can quickly receive acknowledgments and continue operations, but the memory system becomes overloaded and requires frequent throttling operations causing performance degradation and temperature increase

Engineering Contradiction:
Improvecompletion signal output speedVSAvoidmemory system throughput
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The memory controller dynamically adjusts the completion signal output timing based on real-time internal throughput conditions. When throughput is high, the controller delays completion signal output to prevent overload; when throughput is low, it outputs signals promptly. This dynamic adaptation resolves the contradiction between fast signal output and sustained productivity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The memory controller implements a feedback mechanism by monitoring its internal throughput and using this information to control completion signal output timing. The controller continuously adjusts signal output based on feedback about system load, preventing overload while maintaining optimal performance. This feedback loop eliminates the need for frequent throttling operations.

Inventive Principle:
Principle #23Feedback

2Temperature

If the memory controller frequently performs throttling operations to prevent overheating, then the system temperature is controlled, but performance degradation occurs due to reduced operational efficiency

Engineering Contradiction:
Improvememory system temperatureVSAvoidmemory system performance
Core Design Contradiction:
TemperatureVSProductivity

Solution Approach 1:

The memory controller performs preliminary action by proactively delaying completion signal output before the system becomes overloaded. This preventive approach avoids the need for reactive throttling operations that cause performance degradation. By anticipating potential overload conditions and adjusting signal output accordingly, the controller maintains both temperature control and performance.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If the memory controller delays completion signal output to match internal throughput capacity, then throttling operations are reduced and performance is maintained, but the host may experience waiting time increases

Engineering Contradiction:
Improvememory system throughputVSAvoidhost waiting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The delay in completion signal output is not fixed but dynamically adjusted based on internal throughput conditions. The controller only delays signals when necessary to match processing capacity, and outputs signals promptly when capacity is available. This dynamic approach minimizes host waiting time while maintaining system productivity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11086528B2Memory controller and memory system having the same
Publication Date: 2021.08.10 SK HYNIX INC
  • US11086528B2 patent drawing
  • US11086528B2 patent drawing
  • US11086528B2 patent drawing

AI summary

There are provided a memory controller and a memory system having the same. The memory controller includes: a command generator configured to generate a command in response to a request received from a host; a throttling manager configured to activate or inactivate a delay signal by comparing a current throughput of data that is being currently processed in a memory system and a request throughput of data that is to be processed in the memory system; and a completion signal output circuit configured to delay an output of a completion signal with respect to the request when the delay signal is activated, and outputs the completion signal when the delay signal is inactivated.