Memory Controller Time-Based Read Write Phases
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Solution Overview
Problem
Conventional memory subsystems implementing a strict First-Ready, First-Come, First-Served (FRFCFS) policy with read priority suffer from reduced bandwidth due to frequent bus turnarounds and penalties associated with row management, leading to inefficient data bus utilization and increased latency.
Innovation Solution
A time-based scheduling policy is introduced, which includes configurable read and write phases to reduce bus turnarounds and idle times, allowing for improved data bus utilization by prioritizing commands based on their readiness and duration, rather than solely on their arrival order.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strict FRFCFS policy with read priority is implemented, then read commands are processed with high priority, but bus turnaround frequency increases and bandwidth is reduced
Solution Approach 1:
The patent implements dynamic phase switching between read and write operations, transitioning from a static FRFCFS policy to a dynamic time-based scheduling approach. The controller dynamically alternates between executing read commands during read phases and write commands during write phases, optimizing both read priority and overall bandwidth utilization through adaptive phase management
Solution Approach 2:
The patent introduces periodic read phases and write phases that alternate in a structured manner. By organizing command execution into periodic phases with configurable durations, the system ensures regular read access while maintaining write operation throughput, reducing the harmful effects of frequent bus turnarounds through predictable scheduling patterns
2Adaptability or versatility
If frequent bus turnarounds are performed to handle mixed read/write commands, then command flexibility is improved, but idle data bus cycles increase and utilization decreases
Solution Approach 1:
The patent segments the command execution into distinct read phases and write phases, separating mixed read/write operations into dedicated time windows. This segmentation allows the data bus to operate continuously in one direction during each phase, eliminating the need for frequent turnarounds and reducing idle cycles while maintaining the ability to handle both read and write commands effectively
Solution Approach 2:
The patent ensures continuous useful action on the data bus by maintaining active command execution throughout read and write phases. By configuring phase durations to match command completion times and minimizing phase transition overhead, the system maximizes data bus utilization and reduces idle time while preserving command processing flexibility
3Ease of operation
If row management operations are performed frequently to maintain memory state, then memory accessibility is improved, but latency increases due to associated penalties
Solution Approach 1:
The patent performs preliminary row management operations during dedicated phases before command execution. By opening rows in advance during read phases and closing them during write phases, the system prepares memory state proactively, reducing the need for time-critical row operations during active command processing and thereby minimizing latency penalties
Data Source
AI summary
Better command scheduling in a memory controller can help improve memory device bandwidth utilization. A method for command scheduling in a memory controller can include processing commands of exclusively a first command type from a command queue including transmitting data in a first direction using a data bus for a first duration. Responsive to determining the first duration meets or exceeds a specified time or cycle limit, the bus can be turned around to accommodate transactions or commands of a second type. Following the bus turnaround, the method can include processing commands of exclusively a second command type from the command queue including transmitting data in a second direction using the data bus. The time or cycle limit can be statically or dynamically adjusted, for example, based on a read/write mix of commands in the command queue.