Memory Controller Timeout Adaptation for Buffer Capacity
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Solution Overview
Problem
Conventional semiconductor memory systems fail to optimize the execution order of commands from multiple masters based on the varying residual memory capacities of their data buffers, leading to performance deterioration when lower-capacity masters are not serviced promptly.
Innovation Solution
A semiconductor memory device with a memory controller that receives timeout index signals from each master group, sets timeout values based on residual buffer capacities, and adjusts the execution order of commands in the queue to prioritize masters with lower buffer capacity, ensuring timely handling of commands and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If commands are executed based on fixed timeout values for each master group, then system stability is maintained, but performance deteriorates when masters with lower residual buffer capacity are not serviced promptly
Solution Approach 1:
The patent applies dynamics by making the timeout value adaptive rather than fixed. The memory controller dynamically adjusts the timeout value for each master based on real-time monitoring of residual data buffer capacity. When a master's buffer capacity decreases below a threshold, the timeout value is reduced, causing that master's commands to be executed with higher priority. This dynamic adjustment resolves the contradiction by maintaining system stability through structured timeout management while improving performance by adapting to changing buffer conditions.
Solution Approach 2:
The patent changes the parameter of timeout value based on the residual capacity parameter of data buffers. The memory controller monitors the residual capacity and modifies the timeout parameter accordingly - reducing timeout values for masters with low buffer capacity and maintaining higher timeout values for masters with sufficient buffer capacity. This parameter change enables the system to prioritize commands dynamically, improving overall system performance while maintaining stability through controlled parameter adjustment.
2Speed
If timeout values are set to small values for higher priority operations, then real-time operation performance is improved, but control operations may be delayed
Solution Approach 1:
The patent applies local quality by assigning different timeout values to different masters based on their specific buffer conditions and operation types. Instead of using a uniform timeout value for all operations, the memory controller evaluates each master's residual buffer capacity and sets appropriate timeout values locally. This allows real-time operations from masters with low buffer capacity to receive smaller timeout values (higher priority) while control operations from masters with sufficient buffer capacity receive larger timeout values, preventing their delay.
3Productivity
If all masters are serviced in parallel without priority differentiation, then system throughput is maximized, but masters with low buffer capacity experience performance degradation
Solution Approach 1:
The patent applies segmentation by dividing masters into different priority segments based on their residual buffer capacity. The memory controller segments the command execution queue such that masters with buffer capacity below the threshold are placed in a high-priority segment with smaller timeout values, while masters with sufficient buffer capacity are placed in a normal-priority segment with larger timeout values. This segmentation allows the system to maintain high throughput by processing multiple commands in parallel while ensuring quality of service for vulnerable masters through priority-based execution ordering.
Data Source
AI summary
A method of operating a semiconductor memory device includes receiving a timeout index signal corresponding to a master of the first master group based on a residual capacity of a data buffer of the first master, setting a first timeout value in response to the timeout index signal, and changing an execution order of commands stored in a queue of the semiconductor memory device based on a result of counting the first timeout value and counting a second timeout value corresponding to a master of the second master group.