Memory Controller Timing Enforcement via Lookup Tables

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Solution Overview

Problem

There is a need for improved techniques to enforce timing requirements in memory devices, particularly in DRAM systems, to ensure that commands are issued in compliance with specified timing constraints to prevent violations during operations such as read and write operations.

Innovation Solution

A memory subsystem with a controller that enforces timing requirements by maintaining time thresholds for different pairs of event types, using a scheduler to queue and dispatch event commands, and a completed event list to track timestamps, ensuring that commands are only processed after a specified time has elapsed since the last event at the same addressable location.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a lockout feature is implemented to enforce timing requirements, then timing compliance is improved, but device complexity increases

Engineering Contradiction:
Improvetiming complianceVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing timing requirements in a lookup table before operations occur. The timing controller queries this pre-prepared table to determine lockout periods, avoiding complex real-time calculations and reducing operational complexity while maintaining timing compliance.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary timing controller that mediates between the command interface and memory operations. This controller checks timing requirements against a lookup table and enforces lockout periods, isolating the complexity of timing enforcement from the main memory operations and simplifying the overall system architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If timing checks are performed for every command, then timing requirement enforcement is improved, but processing speed deteriorates

Engineering Contradiction:
Improvetiming enforcementVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary anti-action by proactively managing command queuing and timing state before violations can occur. The timing controller monitors operation states and prevents improperly timed commands from being processed, rather than detecting and correcting violations after they occur, thus maintaining both timing enforcement and processing efficiency.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent uses a lookup table that stores pre-determined timing requirements as copies of valid command sequences and their associated lockout periods. Instead of performing complex real-time timing analysis, the system queries this copied timing data, dramatically reducing processing overhead while maintaining accurate timing enforcement.

Inventive Principle:
Principle #26Copying

3Manufacturing precision

If lockout periods are enforced for memory operations, then timing constraints are satisfied, but operational flexibility is reduced

Engineering Contradiction:
Improvetiming constraint satisfactionVSAvoidoperational flexibility
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the memory system's operational state transparent and queryable. The timing controller dynamically tracks operation states (such as refresh-in-progress flags) and uses this dynamic information to make intelligent decisions about command acceptance, allowing the system to be flexible within timing constraints rather than rigidly enforcing fixed lockout periods.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback mechanisms where the timing controller continuously monitors memory operation states and uses this feedback to determine whether lockout periods are currently active. This feedback-driven approach allows the system to adapt command acceptance decisions based on real-time operational status, maintaining timing compliance while maximizing operational flexibility when constraints are not violated.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS10503410B2Apparatus and method for enforcing timing requirements for a memory device
Publication Date: 2019.12.10 INTEL CORP
  • US10503410B2 patent drawing
  • US10503410B2 patent drawing
  • US10503410B2 patent drawing

AI summary

Provided are an apparatus and method for enforcing timing requirements for a memory device. An event command directed to a target addressable location comprising one of the addressable locations is received. A determination is made as to whether a time difference of a current time and a timestamp associated with a completed event directed to a threshold location including the target addressable location exceeds a time threshold. The received event command is executed against the target addressable location in response to determining that the time difference exceeds the time threshold.