Memory Controller Timing Packets for Multi-Die Read Throughput
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Solution Overview
Problem
The increasing operating frequency of flash-based memory systems leads to performance deterioration due to command overhead, particularly in managing data output timing across multiple non-volatile memory dies.
Innovation Solution
A memory controller is designed to manage data output timing by using command packets with delay information to control the sequencing of data output commands, select chip enable packets, and terminate selection commands, optimizing the operation of multiple non-volatile memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of the flash-based memory system is increased, then the data transfer speed is improved, but the command overhead increases causing performance deterioration
Solution Approach 1:
The patent applies preliminary action by including delay information in advance within the select chip enable packet. This allows the memory controller to pre-calculate and embed the required delay period before data output, enabling the memory die to prepare its data output timing in advance rather than waiting for separate control signals, thus reducing command overhead at higher operating frequencies
Solution Approach 2:
The patent extracts the delay control function from separate control packets and integrates it directly into the select chip enable packet. By taking out the delay period specification from the command sequence and embedding it in the chip enable signal itself, the system reduces the number of separate commands needed, lowering overhead while maintaining precise timing control for high-speed operation
2Productivity
If multiple non-volatile memory dies are managed simultaneously, then the data throughput is improved, but the output timing coordination becomes complex causing delays
Solution Approach 1:
The patent applies local quality by providing individualized delay information in the select chip enable packet for each specific memory die. Each die receives customized delay parameters tailored to its specific data readiness timing, allowing precise local control of data output timing for each die while managing multiple dies simultaneously, thus coordinating complex multi-die operations without system-wide timing delays
Solution Approach 2:
The patent uses preliminary action by pre-calculating and embedding the appropriate delay period in each select chip enable packet before the memory die begins data output preparation. This advance timing information allows each memory die to independently coordinate its data output with the controller without requiring complex real-time synchronization, enabling efficient multi-die throughput while simplifying timing coordination
Data Source
AI summary
A storage device includes non-volatile memory dies, and a memory controller that outputs a first data output command address packet and receives first data. The memory controller receives the first data from a first non-volatile memory die through a data bus, and sequentially outputs a second data output command packet that instructs a second non-volatile memory die among the plurality of non-volatile memory dies to output second data, a second select chip enable packet that selects the second non-volatile memory die, and a first select chip terminate command packet that terminates selection of the first non-volatile memory die. The second select chip enable packet includes a header that indicates a select chip enable, a first body that specifies the second non-volatile memory die, and a second body that includes first delay information for delaying an output point in time of the second data.