Memory Controller Timing Packets for Multi-Die Flash Read Throughput
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Solution Overview
Problem
The increasing operating frequency of flash-based memory systems leads to performance deterioration due to command overhead, particularly in managing data output timing across multiple non-volatile memory dies.
Innovation Solution
A memory controller is implemented with command queues and delay mechanisms to manage data output timing by using command packets with delay information, allowing for synchronized and efficient data transfer between multiple non-volatile memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of the flash-based memory system is increased, then the data transfer speed is improved, but the command overhead increases and performance deteriorates
Solution Approach 1:
The patent applies preliminary action by outputting the second data output command packet in advance before the first data output is completed. The memory controller prepares and transmits the command for the second non-volatile memory die while the first die is still outputting data, thereby overlapping command issuance with data transfer operations and reducing overall command overhead.
Solution Approach 2:
The patent implements continuity of useful action by ensuring that command transmission and data output operations overlap in time. The memory controller maintains continuous utilization of the memory system by issuing subsequent commands during the data output phase of previous commands, eliminating idle periods and maintaining productive operations throughout the system.
2Productivity
If data output from multiple non-volatile memory dies is managed sequentially, then command overhead is reduced, but output timing delays increase
Solution Approach 1:
The patent applies dimensionality change by transitioning from sequential management of data output (one die at a time) to parallel management where multiple dies are coordinated simultaneously. The memory controller issues commands to multiple non-volatile memory dies in an overlapping timeframe, utilizing temporal parallelism to reduce overall output timing delays while maintaining organized command flow.
Solution Approach 2:
The patent implements dynamics by making the command output timing flexible and adaptive. The memory controller dynamically adjusts the timing of command packets based on the state of data output from different memory dies, allowing commands to be issued at optimal moments rather than following a rigid sequential schedule, thereby reducing delays without increasing overhead.
3Productivity
If the second data output command packet is output before the first select chip terminate command packet, then read performance is improved, but output timing synchronization becomes complex
Solution Approach 1:
The patent uses an intermediary approach by introducing a command packet structure that includes both the second data output command and the first select chip terminate command in a defined sequence. The memory controller manages the timing relationship between these commands through a structured packet format, which mediates the complex timing requirements by providing a clear protocol for when each command should be issued relative to others.
Data Source
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AI summary
A storage device includes non-volatile memory dies (121, 122), and a memory controller (110) that outputs a first data output command address packet and receives first data. The memory controller (110) receives the first data from a first non-volatile memory die (121) through a data bus, and sequentially outputs a second data output command packet that instructs a second non-volatile memory die (122) among the plurality of non-volatile memory dies (121, 122) to output second data, a second select chip enable packet that selects the second non-volatile memory die (122), and a first select chip terminate command packet that terminates selection of the first non-volatile memory die (121). The second select chip enable packet includes a header that indicates a select chip enable, a first body that specifies the second non-volatile memory die (122), and a second body that includes first delay information for delaying an output point in time of the second data.