Memory Controller Timing Reference Preambles for Idle-Rank Reaccess
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Solution Overview
Problem
In multi-rank memory systems, idle power consumption is high due to inactive ranks, and timing drift and noise from supply voltage fluctuations cause inefficiencies in data transfer, necessitating rapid timing updates before re-accessing idle ranks.
Innovation Solution
A memory controller initiates a timing reference signal (TRS) before data transfer to adjust sampling clocks, using a calibration preamble to compensate for drift and jitter, with fast edge tracking circuits for rapid phase updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If memory ranks are kept inactive to reduce power consumption, then idle power consumption is reduced, but timing drift and noise accumulate causing data transfer inefficiencies
Solution Approach 1:
The patent applies preliminary action by sending a timing reference signal (TRS) before the actual data transfer occurs. When the memory controller detects that a memory rank has been idle for a predetermined period, it first transmits a TRS to realign the timing of the memory device, ensuring that timing drift and noise are compensated before data transfer begins. This preliminary timing alignment prevents data transfer inefficiencies while maintaining power savings during idle periods.
2Measurement precision
If timing reference signal is sent before every data transfer, then timing accuracy is improved, but communication overhead and transfer time increase
Solution Approach 1:
The patent applies local quality by making the timing reference signal transmission selective rather than universal. The memory controller monitors the idle status of each memory rank and only sends a TRS when the rank has been idle for a predetermined period. For actively accessed ranks, no TRS is sent, thus avoiding unnecessary communication overhead. This selective approach ensures timing accuracy is maintained only where needed, while minimizing overall communication time.
Data Source
AI summary
Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.