Memory Controller Topology for Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory system architectures, such as fully-buffered dual-inline memory modules (FB-DIMMs), face high latencies and inefficiencies when multiple DIMMs are connected on the same data channel, leading to increased buffering requirements and scheduling complexities.
Innovation Solution
A memory subsystem architecture where the memory controller is directly coupled to the Nth memory module through a downstream link and receives information from the first memory module through an upstream link, with each memory module connected via downstream and upstream links in a chain configuration, reducing latency and buffering needs by ensuring deterministic delays and efficient frame scheduling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DIMMs are connected on the same data channel in traditional FB-DIMM architecture, then memory capacity is increased, but read latency increases by N*D ns and scheduling complexity increases
Solution Approach 1:
The patent segments the memory system into multiple independent point-to-point channels, each connecting the memory controller directly to individual DIMMs. This segmentation eliminates the shared channel bottleneck and allows parallel independent access to each DIMM, reducing read latency from N*D ns to a fixed small constant regardless of the number of DIMMs in the system.
Solution Approach 2:
The patent introduces point-to-point direct links as intermediaries between the memory controller and each DIMM, eliminating the need for daisy-chained connections through intermediate DIMMs. Each DIMM receives commands and returns data through its own dedicated channel, removing the propagation delay accumulation that occurs in traditional architectures.
2Quantity of substance
If multiple DIMMs are connected on the same data channel, then memory capacity is increased, but buffering requirements and scheduling complexity increase
Solution Approach 1:
By segmenting the memory interconnect into independent point-to-point channels, the patent eliminates the need for complex centralized scheduling of shared resources. Each channel operates independently, allowing simple decentralized scheduling where the memory controller can issue commands to multiple DIMMs simultaneously without coordination overhead.
Solution Approach 2:
Each DIMM in the point-to-point architecture serves itself through its dedicated channel, independently receiving commands and returning data without interfering with other DIMMs. This self-service capability eliminates the need for complex arbitration and scheduling mechanisms required in shared channel architectures.
Data Source
AI summary
A memory subsystem. A memory subsystem includes a memory controller coupled to a processor and a plurality of N memory modules. The memory controller is directly coupled to convey information to the Nth memory module through a downstream link, and is directly coupled to receive information from a first memory module through an upstream link. Each of the memory modules may be coupled to a prior memory module via a downstream link. Information conveyed from the memory controller to a particular memory module is conveyed to the Nth memory module through the downstream link and, as necessary, through additional downstream links to the particular memory module. Each of the memory modules may be coupled to receive data from a subsequent memory module via an upstream link. Information conveyed from a memory module to the memory controller is conveyed from the memory module through upstream links to the memory controller.