Memory Controller Trainer Circuitry for Link Training Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed memory systems face challenges in maintaining accurate data sampling due to narrowing data eyes and thermal condition-induced drift, which conventional link training methods struggle to address efficiently, especially at high data rates above 12 Gbps.
Innovation Solution
The implementation of a memory controller with trainer circuitry that enables link training without BIOS intervention, allowing for efficient access to memory resources and adjustment of operational parameters such as timing and voltage, independent of processor functionality, to maintain data validity during the training process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If link training is performed using conventional BIOS intervention methods, then timing accuracy can be maintained, but system latency increases and operational efficiency decreases
Solution Approach 1:
The patent extracts the link training functionality from the BIOS/processor domain and relocates it to the memory controller domain. The memory controller independently generates and processes training signals without requiring processor intervention, thereby eliminating the latency associated with BIOS-based training while maintaining timing accuracy through dedicated hardware circuits.
Solution Approach 2:
The patent introduces an intermediary training signal generation mechanism within the memory controller that acts as a mediator between the memory device and the processor. This intermediary structure enables direct training operations without involving the processor, reducing system latency while preserving timing precision through specialized training circuits.
2Reliability
If link training is performed frequently to maintain data validity, then data sampling accuracy improves, but system overhead and complexity increase
Solution Approach 1:
The memory controller is designed with multi-functionality, integrating both operational memory control and link training functions within a single device. The training signal generation circuits are incorporated into the existing memory controller architecture, allowing frequent training operations without requiring separate dedicated hardware, thus improving data sampling accuracy while minimizing additional system overhead.
Solution Approach 2:
The memory controller performs link training autonomously without external assistance from the processor or BIOS. The self-service capability allows the memory controller to independently generate training signals, evaluate data validity, and adjust timing parameters as needed, enabling frequent training operations with minimal system overhead and no additional complexity from external controllers.
3Reliability
If processor functionality is disabled during link training, then data validity is maintained, but access to memory resources is restricted
Solution Approach 1:
The patent segments the memory controller's operational modes into distinct functional states: a first mode for normal memory access and a second mode for link training. This segmentation allows the system to switch between modes as needed, maintaining data validity during training by disabling processor access temporarily, then rapidly returning to the access mode to restore memory resource availability, thus balancing reliability and ease of operation.
Data Source
AI summary
Techniques and mechanisms for providing communications which facilitate link training. In an embodiment, a memory controller includes, or couples to, trainer circuitry which is configured to provide instructions to generate memory access commands. The instructions are accessed at the circuitry in response to an indication that link training is performed, where the accessing is independent of communication with a processor coupled to the memory controller. Based on the instructions, memory access commands are communicated via a link between the memory controller and a memory device. Link training is performed based on an evaluation of one or more characteristics of the link communications. In another embodiment, memory access commands are generated, based on the instructions, while a validity of data at the memory device is maintained.