Memory Controller Data Transfer Mapping Logic
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Solution Overview
Problem
Current memory systems face inefficiencies in data transfer operations, particularly when handling data sizes smaller or larger than a preset size, due to limitations in addressing and programming strategies.
Innovation Solution
A memory system configuration involving a controller that divides logical addresses into groups and maps them to reference logical units across multiple memory dies and planes, optimizing data transfer order based on data size, allowing for efficient handling of both small and large data transfers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred using conventional addressing methods in memory systems, then the system can handle standard data sizes, but it becomes inefficient when handling data sizes smaller or larger than preset sizes
Solution Approach 1:
The patent segments logical addresses into multiple divided logical groups and maps them to reference logical units across different dimensions (L-level cell bits, memory dies, planes). This segmentation allows flexible handling of various data sizes by distributing address groups across multiple memory components, thereby improving both transfer efficiency and adaptability to different data size requirements.
Solution Approach 2:
The patent introduces multi-dimensional mapping by organizing reference logical units across three dimensions: L-level cell bits, memory dies, and planes. This dimensional approach transforms the conventional single-dimension addressing into a multi-dimensional address space, enabling efficient data transfer for both small and large data sizes by utilizing the additional organizational layers.
2Productivity
If the memory system uses a simple addressing scheme, then the system complexity is low, but it cannot optimize data transfer for different data sizes across multiple channels
Solution Approach 1:
The addressing mechanism is segmented into multiple components: logical address division into groups, reference logical unit determination across L-level bits/dies/planes, and multi-dimensional mapping. This segmentation allows the system to optimize data transfer by selectively utilizing different segments based on data size, achieving productivity improvement while managing complexity through modular organization.
Solution Approach 2:
The patent implements dynamic addressing where the mapping strategy adapts based on data size. The controller dynamically determines reference logical units and adjusts the mapping configuration across memory dies and planes according to the specific data transfer requirements, enabling optimization without requiring a completely complex static structure.
3Loss of time
If data transfer operations follow a fixed order, then the control logic is simple, but transfer time cannot be minimized for different data sizes
Solution Approach 1:
The patent implements dynamic transfer order determination where the sequence of data transfer is adaptively decided based on data size. The controller dynamically selects the optimal transfer order by mapping divided logical groups to reference logical units across multiple dimensions, minimizing transfer time for each specific data size while managing complexity through algorithmic decision-making.
Solution Approach 2:
The transfer order is determined by changing parameters such as the number of divided logical groups, reference logical unit selection, and mapping configuration across dies and planes. By adjusting these parameters based on data size, the system optimizes transfer time without requiring a completely complex control mechanism, achieving time reduction through parameter adaptation.
Data Source
AI summary
A memory system includes: a memory device including a plurality of pages each including a plurality of L-level cells, K planes each including the plurality of pages, and N memory dies each including the K planes; and a controller suitable for dividing logical addresses corresponding to write data, into a plurality of divided logical groups by grouping the logical addresses by a preset number, when performing a program operation of transferring the write data to the memory device to store, and mapping each of the plurality of divided logical groups to a reference logical unit in a first order of bits of the L-level cell, a second order of the N memory dies, and a third order of the K planes, according to a size of the write data, in order to decide an order in which the write data are to be transferred to the memory device.