Memory Controller Transfer Phase Suspension for Read Latency

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Solution Overview

Problem

In memory systems, there is a challenge to minimize latency for read requests from hosts while efficiently managing data transfer and storage in non-volatile memory, particularly in NAND-type flash memory systems, where existing methods may lead to increased latency due to the need to suspend and resume data transfer phases.

Innovation Solution

The memory controller suspends the data transfer phase in the memory system and executes a read sequence, saving data from the transfer buffer to a backup buffer before resuming the transfer phase, allowing for efficient data handling and reducing latency by avoiding the need to retransfer data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the data transfer phase is suspended to execute a read sequence, then read latency is reduced, but the total program time increases due to phase suspension and resumption overhead

Engineering Contradiction:
Improveread latencyVSAvoidprogram time
Core Design Contradiction:
Loss of timeVSDuration of action of moving object

Solution Approach 1:

The patent applies preliminary action by saving transfer buffer data to a backup buffer before suspending the data transfer phase. This preparation ensures that when the read sequence is executed, the original data can be restored without retransmission, thereby reducing read latency while minimizing the impact on total program time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements discarding and recovering by temporarily moving data from the transfer buffer to a backup buffer during phase suspension, then restoring it after the read sequence completes. This allows the system to prioritize read operations while preserving the original data for continued program operations, effectively managing the trade-off between read latency and program time.

Inventive Principle:
Principle #34Discarding and recovering

2Loss of time

If data is saved and restored frequently to handle read requests during transfer phase, then read latency is reduced, but power consumption increases

Engineering Contradiction:
Improveread latencyVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by selectively saving only the necessary portion of transfer buffer data to the backup buffer when a read request is received during the data transfer phase. This selective approach reduces the overhead of frequent save/restore operations compared to saving entire buffers, thereby lowering power consumption while still achieving low read latency for the specific requested data.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11347398B2Memory system chip that suspends transfer phase and resumes transfer phase
Publication Date: 2022.05.31 KIOXIA CORP
  • US11347398B2 patent drawing
  • US11347398B2 patent drawing
  • US11347398B2 patent drawing

AI summary

According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.