Memory Controller Translating Requests for High Reliability
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Solution Overview
Problem
Current memory solutions for space applications, particularly in radiation-hardened systems, do not match the performance of advanced field programmable gate arrays (FPGAs) due to the use of conventional static random access memory (SRAM) devices with low speeds and large buses, which introduce wait states and are not optimized for high reliability and high-speed operations.
Innovation Solution
The development of memory controllers that enable high-reliability memory devices with double data rate (DDR) read and write buses, utilizing radiation-hardened field programmable gate arrays (FPGAs) and error detection and correction circuits to manage data transfers efficiently, allowing for concurrent read/write operations and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM devices are used in parallel for error correcting/redundancy, then reliability is improved, but device complexity and bus width increase introducing wait states
Solution Approach 1:
The patent extracts the error correction function from the memory array structure itself and implements it through parity bits generated by dedicated parity generation logic. This separates the core memory function from the error correction function, allowing the memory array to operate with a single port while error correction is handled through computational logic that processes data streams independently.
Solution Approach 2:
The patent introduces a controller as an intermediary component between the single-port memory device and the dual-port requirements. The controller manages the complex interaction by buffering data, generating parity bits, and coordinating read/write operations across different clock domains, thereby abstracting the complexity from the memory array itself.
2Reliability
If conventional SRAM devices operate at low speeds, then reliability is maintained, but productivity and data transfer rate deteriorate
Solution Approach 1:
The patent changes the operational parameters by enabling the memory device to function at high speeds (matching modern FPGA clock rates) while maintaining reliability through radiation-hardened design and error correction. The controller dynamically adjusts timing parameters and clock domain crossings to optimize performance while ensuring data integrity through parity verification.
3Reliability
If a large number of SRAM devices are used in parallel, then reliability through redundancy is improved, but speed deteriorates due to wait states
Solution Approach 1:
The patent extracts the redundancy function from parallel hardware implementation and implements it through software-controlled parity generation and verification. This allows the system to maintain reliability through computational redundancy rather than hardware redundancy, eliminating the wait states associated with parallel SRAM arrays.
4Reliability
If radiation hardened memory solutions are used, then reliability in radiation environments is improved, but performance matching advanced FPGAs deteriorates
Solution Approach 1:
The patent ensures continuous high-speed operation by implementing pipeline buffering and asynchronous clock domain crossing. The controller continuously generates parity bits and manages data streams without interruption, maintaining productive action even during error detection and correction operations, thus matching FPGA performance while ensuring radiation-hardened reliability.
Data Source
AI summary
A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein the memory device interface comprises an address output configured to transmit address values, a write data output configured to transmit write data on rising and falling edges of a periodic signal, and a read data input configured to receive read data at the same rate as the write data.