Memory Controller Translation Caching Strategy

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Solution Overview

Problem

Conventional memory systems face inefficiencies in caching translation information in volatile memory, leading to potential data loss during power-offs without proper notification, and require improved methods to manage and update translation information efficiently.

Innovation Solution

A memory system comprising a nonvolatile NAND memory, a volatile RAM, and a memory controller that caches translation information in a buffer, employing techniques like abbreviation and expansion of translation information groups, and eviction processes to efficiently manage and update data, ensuring efficient power-off sequences and data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If translation information is cached in volatile memory, then access speed is improved, but data loss occurs during power-off without notification

Engineering Contradiction:
Improvetranslation information access speedVSAvoiddata integrity during power-off
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The memory controller detects power-off conditions in advance and performs preliminary actions by flushing cached translation information from volatile memory to nonvolatile memory before the power-off completes, preventing data loss

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system monitors power-off notification signals and uses this feedback to trigger the flushing operation, adjusting its behavior based on the detected power state changes

Inventive Principle:
Principle #23Feedback

2Measurement precision

If all translation information is cached in volatile memory, then translation accuracy is improved, but memory usage increases

Engineering Contradiction:
Improvetranslation accuracyVSAvoidvolatile memory usage
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The system applies different caching strategies to different translation information groups based on their characteristics, caching only those that benefit from volatility while keeping others in nonvolatile memory

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Translation information is divided into multiple groups, with the controller selectively caching specific groups in volatile memory based on access patterns and memory availability, rather than caching all translation information

Inventive Principle:
Principle #1Segmentation

3Loss of information

If translation information is updated frequently, then data freshness is improved, but processing time increases

Engineering Contradiction:
Improvetranslation information freshnessVSAvoidupdate processing time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The system extracts and caches only the essential translation information groups that are frequently accessed or recently updated, separating them from the full translation information set to reduce update overhead

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The memory controller performs preliminary flushing of translation information to nonvolatile memory before power-off, ensuring data freshness is maintained without requiring continuous updates during operation

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10216644B2Memory system and method
Publication Date: 2019.02.26 KIOXIA CORP
  • US10216644B2 patent drawing
  • US10216644B2 patent drawing
  • US10216644B2 patent drawing

AI summary

According to one embodiment, a memory system includes a nonvolatile first memory, a second memory which has a buffer, and a memory controller. The memory controller manages a plurality of pieces of translation information. In a case where the plurality of pieces of translation information include a first plurality of pieces of translation information, the memory controller caches first translation information among the first plurality of pieces of translation information and does not cache second translation information among the first plurality of pieces of translation information. The first plurality of pieces of translation information linearly correlates a plurality of continuous physical addresses with a plurality of continuous logical addresses.