Memory Controller Transmission Order Optimization
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Solution Overview
Problem
Current memory systems face challenges in efficiently processing and transmitting data due to operational complexity and performance degradation, particularly in reducing noise and interference during data transfer between memory devices and hosts, which affects the speed and reliability of data reading and writing operations.
Innovation Solution
A memory system with a controller that determines a transmission order based on multiple orders of channels, planes, ways, and bits in multi-level cells, optimizing data transmission by setting logical storage units and using buffers to manage data transfer efficiently across multiple channels and ways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted through multiple channels and ways in parallel, then data transmission speed is improved, but noise and interference between channels increases
Solution Approach 1:
The patent segments data transmission into multiple independent channels and ways, allowing parallel data flow while maintaining isolation between channels. Each channel processes specific data portions separately, reducing mutual interference while achieving high-speed transmission through aggregation of multiple segmented paths.
Solution Approach 2:
The patent applies local quality by optimizing transmission characteristics for each individual channel and way based on its specific conditions. Different channels may use different modulation schemes, coding rates, or power levels tailored to their local signal quality, thereby maximizing overall transmission speed while minimizing noise impact on each channel.
2Reliability
If complex mapping and buffering operations are performed to optimize transmission order, then data transmission reliability is improved, but operational complexity increases
Solution Approach 1:
The patent performs preliminary mapping and buffering operations before actual data transmission. Data is pre-organized into optimal transmission sequences, and buffering is established in advance to handle potential transmission issues. This preliminary preparation ensures reliable data delivery while simplifying the real-time transmission process.
Solution Approach 2:
The patent introduces buffering memory and mapping circuitry as intermediary components between the data source and transmission channels. These intermediaries handle complex reordering, retry logic, and error recovery operations, isolating the complexity from the main transmission path and simplifying overall system operation while maintaining high reliability.
Data Source
AI summary
A memory system includes at least one memory device and a controller coupled with the at least one memory device via plural communication lines. The at least one memory device includes plural units, each unit including plural memory cells, each memory cell capable of storing multi-bit data. The controller determines a hierarchy used for determining an access sequence access to the plural communication lines, the plural units, and plural bits of the multi-bit data, and accesses memory cells included in the at least one memory device based on the hierarchy for a read or write operation regarding transmitted data.