Memory Controller Tree Routing for IPv6 Lookup
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Solution Overview
Problem
Conventional indexing schemes for large memory systems, such as those used in Internet Protocol routers, become impractical for efficient access and storage as the number of memory addresses increases, particularly with the transition from IPv4 to IPv6, which requires more complex and scalable solutions for output port lookup.
Innovation Solution
A memory controller divides memory into multiple banks and creates a tree structure with routing tables accessed via pointers, allowing concurrent access and efficient lookup of target memory addresses based on Internet Protocol addresses, using route packets to update and maintain the data structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional indexing schemes are used for large memory systems, then memory address locations can be accessed, but access efficiency deteriorates as the number of memory addresses increases (particularly with IPv6 transition)
Solution Approach 1:
The patent segments the large memory system into multiple banks (first bank, second bank, etc.) that can be accessed concurrently. Each bank stores a portion of the routing table data, allowing parallel access operations. This segmentation enables the system to handle large numbers of IPv6 addresses while maintaining access efficiency through simultaneous operations on multiple memory banks.
2Adaptability or versatility
If the number of output ports increases to support IPv6, then address coverage improves, but storage complexity increases
Solution Approach 1:
The patent introduces a hierarchical tree structure with multiple levels (root level, intermediate levels, leaf levels) to organize routing table data. This dimensional organization allows the system to accommodate a vast number of IPv6 addresses by distributing data across hierarchical levels and memory banks, reducing storage complexity while maintaining comprehensive address coverage.
3Speed
If concurrent access to multiple memory banks is enabled, then access speed improves, but control complexity increases
Solution Approach 1:
The patent employs memory controllers as intermediary components that manage concurrent access to multiple memory banks. These controllers handle the coordination and control of parallel operations, shielding the upper-level routing logic from the complexity of low-level memory management. This intermediary approach enables high-speed concurrent access while containing control complexity within dedicated memory management components.
Data Source
AI summary
In a system, a memory controller separates a memory into multiple banks and enables a plurality of selected banks to be accessed concurrently. The memory controller further comprises a logic that creates a representation of a tree structure in memory and builds routing tables accessed by pointers at nodes in the tree memory structure, and a logic that finds a target memory address based on a received Internet Protocol (IP) address used by the tree memory structure and the routing table.