Memory Controller Two-Stage ECC for SSD Storage Capacity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing size of physical blocks in nonvolatile memory systems reduces the number of physical blocks, making it challenging to maintain a low ratio of error correction codes (ECCs) while ensuring data integrity and storage capacity, particularly in solid-state drives (SSDs) with NAND flash memory, where the number of physical blocks needed to be secured simultaneously increases, affecting write performance and error correction efficiency.
Innovation Solution
The memory system employs a controller that writes data in a manner where physical blocks are supplied one by one as host write destinations, using intermediate ECCs for incomplete media blocks and final ECCs for complete media blocks, allowing for reduced ECC overhead while maintaining error correction capabilities, and manages block transitions through garbage collection to optimize storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of physical blocks is increased, then the storage capacity is improved, but the number of physical blocks decreases making it harder to maintain low ECC ratio
Solution Approach 1:
The patent segments the error correction process into two distinct stages: intra-block ECC for individual physical blocks and inter-block ECC across complete media blocks. This segmentation allows the system to handle larger physical blocks by providing granular error correction at the block level while maintaining overall data integrity through the second stage of correction, thereby managing ECC complexity in systems with fewer, larger blocks
Solution Approach 2:
The patent introduces an intermediary two-stage ECC mechanism that acts as a mediator between the increased physical block size and the need for error correction. The first ECC operates within individual blocks as an intermediary layer, while the second ECC operates across complete media blocks, providing a structured approach to managing error correction in systems with larger physical blocks
2Quantity of substance
If the number of physical blocks is decreased, then the storage capacity per block is improved, but the number of blocks needed to be secured simultaneously increases
Solution Approach 1:
The patent applies preliminary action by preparing and managing complete media blocks in advance through the two-stage ECC structure. By organizing physical blocks into complete media blocks with pre-configured error correction mechanisms, the system reduces the number of blocks that need to be simultaneously secured during write operations, thereby improving write performance while maintaining large storage capacity per block
Solution Approach 2:
The patent introduces dynamic block management where physical blocks are dynamically organized into complete media blocks. The system can flexibly manage the transition from individual physical blocks to complete media blocks, allowing optimized write operations that don't require securing all blocks simultaneously, thus improving productivity while maintaining large block capacity
3Quantity of substance
If the ratio of ECCs is reduced, then the storage efficiency is improved, but the error correction capability is compromised
Solution Approach 1:
The patent segments error correction into two stages with different ECC ratios applied at different levels. The first intra-block ECC operates with a lower ratio on individual physical blocks, while the second inter-block ECC operates across complete media blocks. This segmentation allows the system to achieve high user data storage ratio while maintaining comprehensive error correction capability through the combined effect of both stages
Solution Approach 2:
The patent changes the parameters of error correction by applying different ECC ratios at different organizational levels. The first ECC uses one ratio for physical blocks while the second ECC uses a different ratio for complete media blocks. This parameter change strategy allows optimization of storage efficiency while maintaining data integrity through multi-level error correction
4Productivity
If intermediate ECCs are used for incomplete media blocks, then the write performance is improved, but the ECC management complexity increases
Solution Approach 1:
The patent applies dynamic ECC management where the system transitions from using intermediate ECCs for incomplete media blocks to final ECCs when blocks are complete. This dynamic approach allows the system to optimize write performance by using intermediate ECCs during the building phase while automatically switching to the more robust final ECC structure when complete media blocks are formed, with the complexity managed through automated state transitions
Data Source
AI summary
According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n−1 data portions of a first unit that are included in n−1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n−1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n−1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.