Memory Controller Two-Stage Program Operation Balancing
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Solution Overview
Problem
Current memory systems face inefficiencies in write performance due to the time disparity between the first-stage and second-stage command sequences in foggy-and-fine program operations, leading to reduced bus occupation and memory chip operating rates.
Innovation Solution
The memory system employs a configuration where the first-stage command sequence executes a foggy program operation and a part of the fine program operation, while the second-stage command sequence completes the remaining fine program operation, balancing the time required for both sequences and optimizing bus and memory chip utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the first-stage command sequence executes only the foggy program operation and the second-stage command sequence executes the fine program operation, then the program operation can be completed in two stages, but the time required for each stage becomes unbalanced leading to reduced bus occupation and memory chip operating rates
Solution Approach 1:
The fine program operation is segmented into two parts: the first part is executed in the first-stage command sequence along with the foggy program operation, and the second part is executed in the second-stage command sequence. This segmentation balances the execution time across both stages, preventing idle time and improving overall write performance.
Solution Approach 2:
The foggy program operation and the first part of the fine program operation are merged into the first-stage command sequence. This merging allows both operations to be executed in parallel or sequentially within the same stage, optimizing the utilization of the memory chip and bus without creating significant time disparity between stages.
2Productivity
If the first-stage command sequence executes a longer operation including foggy and part of fine program operation, then the memory chip operating rate is maintained high, but the command sequence complexity increases
Solution Approach 1:
The first-stage command sequence is designed to execute the foggy program operation followed by the first part of the fine program operation in a predetermined sequence. This preliminary structuring of operations allows the memory chip to remain busy throughout the first stage, maintaining high operating rates while the controller prepares the second-stage command sequence.
3Loss of time
If the two-stage program operation is implemented with balanced execution times, then bus occupation is optimized, but the control logic complexity increases
Solution Approach 1:
The command sequence structure is made dynamic by allowing the first-stage command sequence to execute variable portions of the fine program operation based on operation progress. This dynamic adjustment enables balanced execution times across stages, optimizing bus occupation while the controller manages the complexity through adaptive command sequencing.
Data Source
AI summary
In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.