Memory Controller Two-Stage Write for Disturbance Suppression
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Solution Overview
Problem
Existing memory systems face challenges in precisely writing 4-bit data to memory cell transistors due to disturbances during write operations, leading to potential incorrect data storage and variations in write operation latency, especially at the boundary between memory blocks.
Innovation Solution
A memory system that performs write operations in two stages: a first write operation followed by a second write operation, where the memory controller instructs the semiconductor device to execute these operations in a specific order across different memory strings, ensuring precise data writing and minimizing the impact of disturbances and latency variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single write operation is performed to store multi-bit data in memory cell transistors, then the write operation speed is maintained, but data writing precision deteriorates due to disturbances during the write operation
Solution Approach 1:
The patent divides a single write operation into two sequential stages: a first write operation that writes initial data to memory cell transistors, and a second write operation that writes correction data to the same memory cell transistors. This segmentation allows the system to first establish baseline data and then apply corrections to compensate for disturbances, thereby improving data writing precision without requiring a complete rewrite of all data.
Solution Approach 2:
The patent performs preliminary actions by executing the first write operation to establish initial data in memory cell transistors before performing the second write operation. The second write operation uses information from the first write operation to determine correction data, allowing the system to proactively compensate for potential disturbances rather than reacting to errors after they occur.
2Reliability
If write operations are performed on all memory cell transistors sequentially, then data writing precision is maintained, but write operation latency varies significantly at boundaries between memory blocks
Solution Approach 1:
The patent segments the write operation into two distinct phases: a first write operation that processes all memory cell transistors to establish initial data, and a second write operation that processes only those memory cell transistors requiring correction. This segmentation reduces the scope of the second operation, thereby reducing latency variation at memory block boundaries while maintaining data integrity.
Solution Approach 2:
The patent applies partial action by performing the second write operation only on memory cell transistors that require correction based on disturbance detection, rather than rewriting all memory cell transistors. This selective approach reduces unnecessary write operations at memory block boundaries, thereby reducing latency variation while maintaining data integrity.
3Quantity of substance
If multi-bit data is stored in a single storage element for high integration, then storage capacity increases, but susceptibility to disturbances during write operations increases
Solution Approach 1:
The patent segments the write operation into two stages, allowing the system to first write multi-bit data to high-capacity storage elements and then apply correction data to compensate for disturbances. This segmentation enables the system to maintain high storage capacity while mitigating the increased susceptibility to disturbances that comes with storing multiple bits in single storage elements.
Solution Approach 2:
The patent implements a feedback mechanism where the system monitors write operations on multi-bit storage elements and uses the results to determine whether correction data is needed. This feedback loop allows the system to dynamically apply corrections only when disturbances are detected, thereby maintaining high storage capacity while reducing the impact of disturbance susceptibility.
Data Source
AI summary
According to one embodiment, a memory system includes a semiconductor memory device including a first and second string each including cells coupled in series, and a memory controller configured to instruct the device to execute a write operation for writing data on any one of the cells in the first or second string. The first and second string are coupled in parallel between a bit line and a source line, and coupled to different word lines. The write operation includes a first write operation and a second write operation executed after the first write operation. The controller is configured to instruct the device to execute a first write operation on a second cell in the second string between a first write operation on a first cell in the first string and a second write operation on the first cell.