Memory Controller UNMAP Command Segmentation
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Solution Overview
Problem
The UNMAP command in memory systems, such as SSDs, requires significant time to process wide-range data invalidation, leading to delays in executing subsequent commands and potential data loss during power failures due to the need for nonvolatile management and wear prevention.
Innovation Solution
A memory controller architecture that divides the UNMAP command process into reservation and background stages, allowing immediate execution of subsequent commands and prioritizing invalidation of accessed regions, with on-demand processing and power failure recovery mechanisms to ensure efficient data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the UNMAP command is executed for a wide range of logical addresses, then data invalidation is achieved, but processing time increases significantly and subsequent commands cannot be executed immediately
Solution Approach 1:
The patent segments the UNMAP command processing into two independent parts: (1) reservation processing that immediately registers the invalidation request and returns to the host, and (2) background processing that actually dissolves the address correspondence relationships. This segmentation allows the host to proceed with other commands while the invalidation completes in the background, resolving the time delay issue.
Solution Approach 2:
The patent performs preliminary action by having the reservation processing unit register the invalidation request and update management information before the actual address dissolution occurs. This preliminary registration ensures data integrity is prepared in advance, allowing the background processing to complete without blocking subsequent commands.
2Reliability
If management information is updated to be nonvolatile for each cluster to prevent data loss and wear, then data integrity is ensured, but processing complexity and time increase
Solution Approach 1:
The patent separates management information updates into two segments: critical metadata (invalidation requests, valid cluster counters) updated immediately in reservation processing, and detailed address correspondence updates performed gradually in background processing. This reduces the complexity burden on any single processing stage.
Solution Approach 2:
The background processing unit autonomously performs the address dissolution and management information updates without requiring host intervention or blocking other commands. The system serves itself by handling the complex updates in the background while the reservation layer provides simple, fast registration.
3Measurement precision
If the controller waits for UNMAP command completion before responding, then processing accuracy is ensured, but command execution speed decreases
Solution Approach 1:
The patent divides the response mechanism into two segments: the reservation processing unit provides an immediate response to the host confirming request reception, while the background processing unit continues accuracy-critical address dissolution without blocking the response. This allows speed and accuracy requirements to be satisfied at different processing stages.
Solution Approach 2:
The reservation processing unit acts as an intermediary that immediately acknowledges the UNMAP request to the host, decoupling the response timing from the actual invalidation completion. This intermediary layer maintains processing accuracy through proper registration while enabling fast response times.
Data Source
AI summary
A memory controller according to the embodiment includes a front-end unit that issues an invalidation command in response to a command from outside of the memory controller, the command including a logical address, an address translation unit that stores a correspondence relationship between the logical and a physical address, an invalidation command processing unit that, when the invalidation command is received, registers the logical address associated with the invalidation command as an invalidation registration region in an invalidation registration unit and issues a notification to the front-end unit, and an internal processing unit that dissolves a correspondence relationship between the logical address registered in the invalidation registration unit and the physical address in the address translation unit in a predetermined order by referencing the logical address registered in the invalidation registration unit. The front-end unit transmits completion command which indicates the completion of the command in response to the notification.