Memory Controller Remapping Unrepairable Defective Rows
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Solution Overview
Problem
Existing memory systems face challenges in increasing the usability of defective memory cell rows, particularly when the defects exceed the available redundancy resources in the redundancy region.
Innovation Solution
A memory system and method that allocate a portion of the normal cell region as a reserved region and remap unrepairable addresses to consecutive physical addresses within this reserved region, thereby bypassing defective memory cell rows and enhancing system usability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundancy resources are used to repair defective memory cell rows, then reliability is improved, but the number of repairable defects is limited by available redundancy resources
Solution Approach 1:
The memory system segments the address space into normal addresses and unrepairable defective addresses. The redundancy region is used to repair some defective rows, while unrepairable defective rows are handled separately through remapping to reserved regions in the normal cell array. This segmentation allows the system to accommodate both repairable and unrepairable defects without limiting overall capacity.
Solution Approach 2:
The patent introduces a new dimension of address management by creating reserved regions within the normal cell array specifically for remapping unrepairable defective addresses. This adds a layer of address translation beyond the traditional redundancy approach, enabling the system to handle defects that exceed redundancy resources while maintaining full addressable capacity.
2Ease of operation
If defective memory cell rows are bypassed using traditional redundancy methods, then usability is improved, but capacity is reduced when defects exceed redundancy resources
Solution Approach 1:
The system performs preliminary identification of unrepairable defective addresses during manufacturing testing and stores them in a defect database. Reserved regions are pre-allocated in the normal cell array based on this defect information. When hosts access memory, the remapping engine automatically translates unrepairable defective addresses to the pre-prepared reserved regions, enabling seamless operation without capacity loss.
3Adaptability or versatility
If unrepairable defective addresses are remapped to non-consecutive physical addresses, then address translation flexibility is improved, but host access performance deteriorates due to address discontinuity
Solution Approach 1:
The patent applies homogeneity by remapping unrepairable defective addresses to consecutive physical addresses within reserved regions. This creates a uniform, contiguous address space for remapped addresses, eliminating the performance penalty of scattered address translation. The remapping engine maintains a mapping table that translates logical unrepairable addresses to consecutive physical addresses in the reserved region, ensuring both flexibility and performance.
Data Source
AI summary
A memory system includes a memory module and a memory controller to control semiconductor memory devices in the memory module. Each of the semiconductor memory devices provides the memory controller with an address of at least a defective memory cell row unrepairable with a redundancy resource in a memory cell array as unrepairable address information. The memory controller allocates a portion of a normal cell regions of at least one of the semiconductor memory devices as a reserved region, and remaps first and second unrepairable addresses to first and second physical addresses of the reserved region in response to first and second host physical addresses from a host matching the first and second unrepairable addresses, respectively. The first physical address and the second physical address are consecutive.