Memory Controller Valid Data Refresh Timing
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Solution Overview
Problem
Dynamic random access memory (DRAM) systems require periodic refresh operations due to leakage paths around transistors and capacitors, which can reduce efficiency and increase power consumption, especially as system memory capacity increases.
Innovation Solution
A memory controller with a storage circuit and control circuit that maintains a data table indicating valid data in each memory block, allowing for differentiated refresh timing based on the validity of data stored, where blocks with valid data are refreshed after a first waiting time and those without or with invalid data are refreshed after a shorter second waiting time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic refresh operations are performed on all memory blocks, then data validity is maintained, but system efficiency decreases and power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on individual memory block characteristics. The data table tracks validity status for each memory block, enabling the controller to apply refresh operations selectively rather than uniformly across all blocks. This localized approach maintains data validity where needed while avoiding unnecessary operations elsewhere, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent implements partial action by performing refresh operations only on memory blocks that contain valid data, as indicated in the data table. Instead of refreshing all memory blocks periodically (excessive action), the system performs partial refresh operations only where necessary, reducing overall refresh overhead while maintaining data integrity for active memory blocks.
2Reliability
If refresh operations are performed on all memory blocks, then data validity is maintained, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on individual memory block characteristics. The data table tracks validity status for each memory block, enabling the controller to apply refresh operations selectively rather than uniformly across all blocks. This localized approach maintains data validity where needed while avoiding unnecessary operations elsewhere, resolving the contradiction between reliability and productivity.
Solution Approach 2:
The patent implements partial action by performing refresh operations only on memory blocks that contain valid data, as indicated in the data table. Instead of refreshing all memory blocks periodically (excessive action), the system performs partial refresh operations only where necessary, reducing overall refresh overhead while maintaining data integrity for active memory blocks.
3Device complexity
If uniform waiting time is used for all refresh operations, then control is simplified, but overall refresh efficiency decreases
Solution Approach 1:
The patent applies dynamics by making the waiting time parameter adaptive rather than static. The controller dynamically adjusts waiting time based on memory block status: using a first waiting time for blocks with valid data and a second waiting time for blocks without valid data. This dynamic control approach improves refresh efficiency while maintaining manageable complexity through the use of a data table for status tracking.
Solution Approach 2:
The patent segments the refresh operation into two distinct pathways based on memory block status. By dividing the refresh process into different waiting time scenarios (first waiting time for valid data blocks, second waiting time for invalid data blocks), the system optimizes overall efficiency while keeping control logic organized through segmentation.
Data Source
AI summary
A memory controller accessing a memory including a plurality of blocks is provided. The memory controller includes a storage circuit and a control circuit. The storage circuit stores a refresh value and a data table. The data table has a plurality of bits. Each bit indicates whether a corresponding block has valid data. The control circuit selects a specific block according to the refresh value and determines whether the specific block stores valid data according to the data table. When the specific block stores valid data, the control circuit accesses the memory after a first waiting time. When the specific block does not store any data or stores invalid data, the control circuit accesses the memory after a second waiting time. The second waiting time is shorter than the first waiting time.