Memory Controller ECC with Variable Block Coverage
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Solution Overview
Problem
Modern memory devices face increasing errors due to smaller device sizes, higher array densities, and increased usage, leading to reduced data reliability and slower operation, as existing error correction codes (ECC) struggle to keep pace with the rising number of errors while maintaining storage space and operational speed.
Innovation Solution
The solution involves decoupling user data structures from ECC data size and algorithm, allowing for variable ECC data block sizes and encoding schemes to increase error coverage and correction capabilities, such as combining multiple sectors under a single ECC code, thereby averaging bit errors over a larger data area without significantly increasing ECC code storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional per-sector ECC is used, then ECC code storage space is minimized, but error detection and correction capability is insufficient for modern high-density memory devices
Solution Approach 1:
The patent combines multiple sectors (e.g., 4 sectors of 512 bytes each) into a single ECC data block of 2048 bytes, allowing one ECC code to protect multiple sectors. This merging approach increases error detection and correction capability across the combined data block while maintaining efficient use of ECC storage space by eliminating redundant per-sector ECC overhead.
2Reliability
If ECC code size is increased to correct more errors, then data reliability improves, but operational speed decreases due to time-consuming error correction algorithms
Solution Approach 1:
The patent segments the error correction process by organizing data into variable-sized ECC data blocks (e.g., 2048-byte blocks containing multiple sectors) that can be processed independently. This segmentation allows the system to apply error correction algorithms at an optimized block level, improving operational speed by avoiding unnecessary processing of entire larger memory structures while maintaining reliable error correction within each block.
3Adaptability or versatility
If fixed per-sector ECC structure is used, then system complexity is minimized, but adaptability to different error patterns and memory configurations is reduced
Solution Approach 1:
The patent implements dynamic ECC data block sizing where the ECC structure can be configured to cover variable numbers of sectors (e.g., 1, 2, 4, or more sectors per ECC block). This dynamic configuration allows the system to adapt to different error patterns, memory densities, and performance requirements without requiring multiple fixed ECC structures, thereby improving versatility while managing complexity through a unified variable-size framework.
Data Source
AI summary
Memory controllers having a data buffer coupled to receive and hold data from a memory device, and an Error Correction Code (ECC) generator/checker coupled to the data buffer. The ECC generator/checker is configured to generate ECC codes for the data and to compare the generated ECC codes with ECC codes received with the data. The memory controllers are configured to permit different ECC coverage area sizes and/or different ECC code types for different portions of the memory device.