Memory Controller Vector Search for LLM Data Processing

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Solution Overview

Problem

The increasing size of artificial intelligence models requires efficient data processing and storage solutions, particularly for Large Language Models (LLMs), where frequent training is not allowed, and immediate reflection of additional information is needed, posing challenges in storage and processing speed.

Innovation Solution

A data processing acceleration apparatus comprising a hardware accelerator, memory device, and memory controller, which includes multiple computing units and interfaces for efficient communication protocols, enabling vector search processes and output generation for LLMs, with the memory device storing vector databases and operating as a cache for storage devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the size of artificial intelligence models increases to handle more data, then the processing capability and data handling capacity improve, but the storage space requirement increases and processing speed decreases

Engineering Contradiction:
Improvedata processing capabilityVSAvoidstorage space requirement
Core Design Contradiction:
ProductivityVSVolume of stationary object

Solution Approach 1:

The system divides the data processing function into separate components: a host processor for general tasks, a hardware accelerator (NPU/GPU) for AI model execution, and a memory controller with computing units for vector search. This segmentation allows each component to be optimized independently, enabling the storage of large AI models while maintaining processing speed through specialized hardware.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory controller acts as an intermediary between the host processor and the hardware accelerator, managing data transfer and coordinating operations. The computing units within the memory controller perform vector search operations locally, reducing the need for data to travel between components and thereby maintaining high processing speeds despite increased storage requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Stability of the object's composition

If frequent training of artificial intelligence models is not allowed, then the model stability is maintained, but the ability to reflect additional information decreases

Engineering Contradiction:
Improvemodel stabilityVSAvoidability to reflect additional information
Core Design Contradiction:
Stability of the object's compositionVSAdaptability or versatility

Solution Approach 1:

The system pre-stores additional information in a vector database within the memory device before it is needed. When new information becomes available, it can be immediately queried and retrieved without requiring retraining of the AI model. The computing units perform vector search operations to find relevant information, enabling the system to adapt to new data while maintaining model stability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The vector database serves as an intermediary storage layer between the stable AI model and the dynamic external information sources. The memory controller mediates between the model execution and information retrieval, allowing the system to incorporate additional information through vector search rather than model retraining, thus maintaining both stability and adaptability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If a database is constructed to store additional information for artificial intelligence models, then the adaptability to reflect additional information improves, but the storage space requirement increases

Engineering Contradiction:
Improveability to reflect additional informationVSAvoidstorage space requirement
Core Design Contradiction:
Adaptability or versatilityVSVolume of stationary object

Solution Approach 1:

The memory device stores the vector database locally within the data processing acceleration apparatus, optimizing access patterns for the hardware accelerator. This local storage enables efficient retrieval of additional information without requiring extensive external storage infrastructure, thereby reducing overall storage space requirements while maintaining high adaptability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The vector database acts as an intermediary layer that efficiently stores and retrieves additional information. By optimizing the storage structure and access mechanisms within the memory device, the system minimizes the storage space required while maintaining the ability to quickly reflect additional information through vector search operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Speed

If vector search operations are performed to retrieve additional information, then the processing speed for information retrieval improves, but the complexity of the processing system increases

Engineering Contradiction:
Improveinformation retrieval speedVSAvoidprocessing system complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory controller merges multiple functions into a single integrated component: it manages data transfer between host and accelerator, performs vector search operations using dedicated computing units, and coordinates hardware accelerator tasks. This merging reduces the number of separate components and interfaces, thereby reducing overall system complexity while maintaining high information retrieval speed through optimized local processing.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250021551A1Data processing acceleration apparatus
Publication Date: 2025.01.16 XCENA INC
  • US20250021551A1 patent drawing
  • US20250021551A1 patent drawing
  • US20250021551A1 patent drawing

AI summary

A data processing acceleration apparatus is disclosed. The data processing acceleration apparatus comprises a hardware accelerator, a memory device, and a memory controller configured to control the hardware accelerator and the memory device. And the memory controller includes a plurality of computing units, a first interface configured to communicate with a host processor based on a first protocol, a second interface configured to communicate with the memory device based on a second protocol, and a third interface configured to communicate with the hardware accelerator based on a third protocol.