Memory Controller Virtual Address Translation for Shared Physical Memory

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Solution Overview

Problem

Autonomous computing resources in computing devices face challenges in coexisting and sharing resources within a common physical memory domain due to limited physical address bits and independent memory management, leading to inefficient resource allocation and security issues.

Innovation Solution

A memory controller is introduced to manage and allocate physical memory across multiple autonomous compute and I/O elements, providing transparent operation without altering applications or operating systems, and enabling virtual address space translation to physical addresses, along with additional address translations, to enhance resource allocation, security, and sharing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If autonomous computing resources manage memory address space and memory domain at the physical memory level, then each computing resource can independently control its memory, but multiple computing resources cannot coexist to share resources in a common physical memory domain

Engineering Contradiction:
Improveindependent memory managementVSAvoidresource sharing capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent introduces a memory management unit (MMU) as an intermediary component between autonomous computing resources and physical memory. The MMU translates virtual addresses from multiple computing resources into physical addresses, enabling resource sharing while maintaining independent memory management. Each computing resource retains its own address space and memory control, while the MMU coordinates access to the common physical memory domain, resolving the contradiction between independence and sharing capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If computing resources are assigned virtual memory spaces within physical memory, then resource allocation flexibility improves, but address translation complexity increases

Engineering Contradiction:
Improveresource allocation flexibilityVSAvoidaddress translation mechanism
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements address translation by segmenting the memory management function into distinct components within the MMU. The virtual address space is divided into manageable segments or pages, with separate translation tables for different computing resources. This segmentation approach enables flexible virtual memory space assignment while keeping the translation mechanism organized and manageable, reducing the perceived complexity through structured decomposition of the translation process.

Inventive Principle:
Principle #1Segmentation

3Productivity

If multiple autonomous computing resources share physical memory, then resource utilization efficiency improves, but security and access control challenges increase

Engineering Contradiction:
Improveresource utilization efficiencyVSAvoidmemory access security
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by providing customized memory access permissions and translation rules for each computing resource. The MMU maintains separate translation tables and access control lists tailored to each resource's specific security requirements. This allows different security policies to be applied locally to different computing resources while they share the same physical memory, enabling high resource utilization while maintaining individual security boundaries through resource-specific access control mechanisms.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10394707B2Memory controller with memory resource memory management
Publication Date: 2019.08.27 HEWLETT PACKARD ENTERPRISE DEV LP
  • US10394707B2 patent drawing
  • US10394707B2 patent drawing
  • US10394707B2 patent drawing

AI summary

In an example implementation according to aspects of the present disclosure, a memory controller is disclosed. The memory controller is communicatively coupleable to a memory resource having a plurality of memory resource regions, which may be associated with a plurality of computing resources. The memory controller may include a memory resource interface to communicatively couple the memory controller to the memory resource and a computing resource interface to communicatively couple the memory controller to the plurality of computing resources. The memory controller may further include a memory resource memory management unit to manage the memory resource.