Memory Controller Virtual Channel Priority Mapping

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Solution Overview

Problem

Current memory systems face challenges in efficiently managing communication priorities between information processing devices and nonvolatile memory systems, particularly in ensuring Quality of Service (QoS) by effectively utilizing virtual channels according to different specifications like PCIe and NVMe.

Innovation Solution

The memory system employs a controller that manages priority relation information to associate virtual channels with specific priorities, allowing communication information to be transmitted and received based on these priorities, using a combination of PCIe and NVMe specifications to optimize virtual channel usage and command processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If communication information is transmitted without priority-based virtual channel assignment, then device complexity is reduced, but Quality of Service (QoS) deteriorates

Engineering Contradiction:
ImproveQuality of ServiceVSAvoidcontroller complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The communication interface is segmented into multiple virtual channels (VC0-VC7) with distinct priority levels. Each virtual channel is assigned a specific priority value (0-7), allowing communication information to be segmented and transmitted through appropriate channels based on priority requirements. This segmentation enables QoS differentiation without requiring complete redesign of the communication architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller pre-establishes priority relation information that maps NVMe priority values to PCIe virtual channel identifiers before communication occurs. This preliminary assignment of priority relationships allows the system to automatically route communication information through appropriate virtual channels without real-time complex decision-making, reducing operational complexity while maintaining QoS.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If priority relation information is managed in the controller, then Quality of Service is improved, but device complexity increases

Engineering Contradiction:
Improvetransaction efficiencyVSAvoidcontroller complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The controller pre-establishes priority relation information that maps NVMe priority values to PCIe virtual channel identifiers before communication occurs. This preliminary assignment of priority relationships allows the system to automatically route communication information through appropriate virtual channels without real-time complex decision-making, reducing operational complexity while maintaining QoS.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The priority relation information acts as an intermediary data structure that bridges NVMe priority values and PCIe virtual channel identifiers. This intermediary mapping table simplifies the translation process between different protocol priority systems, enabling efficient transaction processing without requiring complex real-time priority arbitration logic in the controller.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If virtual channels are used according to PCIe specification, then adaptability is improved, but ease of operation deteriorates

Engineering Contradiction:
Improvespecification compatibilityVSAvoidvirtual channel management
Core Design Contradiction:
Adaptability or versatilityVSEase of operation

Solution Approach 1:

The controller is designed to handle both PCIe and NVMe protocols simultaneously, with the priority relation information structure serving both specification requirements. The virtual channel assignment mechanism works universally for different types of communication information (commands, data, completions) while maintaining compliance with both PCIe and NVMe specifications, eliminating the need for separate management mechanisms.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11036659B2Memory system for receiving communication information from external device via virtual channels and control method of memory system
Publication Date: 2021.06.15 KIOXIA CORP
  • US11036659B2 patent drawing
  • US11036659B2 patent drawing
  • US11036659B2 patent drawing

AI summary

According to one embodiment, a memory system includes a nonvolatile memory (NVM) and a controller. The controller communicates with an external device via virtual channels (VC) defined in PCI Express Base Specification (PCIe). The external device communicates with the NVM of the memory system per NVM Express Base Specification (NVMe). The controller manages a set of priority relation information (PRI), which maps each priority of Weighted Round Robin with Urgent Priority Class Arbitration mechanism defined in NVMe, to a specific VC. Using the PRI, the controller ensures that the same VC is used throughout the command execution transactions. Quality of Service of communication between the external device and the memory system can thus be improved.