Memory Controller Wear Leveling and Voltage Compensation

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Solution Overview

Problem

The complexity and performance deterioration of memory systems in data processing, particularly due to repetitive read operations and uneven wear across memory blocks, lead to reduced reliability and efficiency in data storage and retrieval.

Innovation Solution

A memory system with a controller that monitors and manages parameters such as read and program counts, temperature, and voltage offsets across memory blocks, performing adaptive read operations and data reclamation to maintain optimal performance by selecting suitable memory blocks and compensating read voltages, thereby minimizing wear and maintaining data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If read operations are performed repeatedly on memory blocks, then data access speed is improved, but read disturbance increases causing performance deterioration and reliability reduction

Engineering Contradiction:
Improvedata access speedVSAvoiddata storage reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The controller proactively monitors read counts and identifies memory blocks that have reached a predetermined read threshold before actual read disturbance occurs. By performing wear leveling and data migration in advance, the system prevents performance deterioration and reliability issues rather than reacting after damage occurs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The controller continuously monitors read operation counts for each memory block and uses this feedback to dynamically adjust block selection for wear leveling operations. When a block approaches the read threshold, the controller receives feedback about its wear state and initiates migration to balanced blocks, creating a closed-loop control system that maintains reliability.

Inventive Principle:
Principle #23Feedback

2Duration of action of stationary object

If wear leveling is performed across all memory blocks, then lifespan is extended, but system complexity increases

Engineering Contradiction:
Improvememory block lifespanVSAvoidcontroller complexity
Core Design Contradiction:
Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

Instead of uniformly applying wear leveling to all memory blocks, the controller monitors each block's read count individually and applies wear leveling operations selectively only to blocks that have reached the predetermined read threshold. This localized approach extends lifespan where needed while minimizing unnecessary operations and complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The controller uses a predetermined read threshold parameter to determine when wear leveling should be applied. By changing the operational state based on this parameter threshold, the system simplifies decision-making logic - blocks are either monitored for threshold crossing or actively managed through migration, reducing overall system complexity.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If voltage offset compensation is applied to all memory blocks, then read accuracy is improved, but processing time increases

Engineering Contradiction:
Improveread voltage accuracyVSAvoidread operation time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The controller applies voltage offset compensation selectively based on the wear state and read count of individual memory blocks. Blocks that have experienced significant read operations or are being migrated receive voltage compensation to ensure accurate reading during transitions, while blocks in stable state use standard read voltages, optimizing both accuracy and speed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10388387B2Memory system and operating method of memory system
Publication Date: 2019.08.20 SK HYNIX INC
  • US10388387B2 patent drawing
  • US10388387B2 patent drawing
  • US10388387B2 patent drawing

AI summary

A memory system includes: a memory device including a plurality of memory blocks each including a plurality of pages suitable for storing data; and a controller suitable for receiving a plurality of commands from a host, performing a plurality of command executions on the plurality of memory blocks in response to the plurality of commands, checking parameters of the plurality of memory blocks according to the plurality of command executions performed on the plurality of memory blocks, selecting first memory blocks among the plurality of memory blocks according to the parameters, and copying data stored in the first memory blocks to second memory blocks among the plurality of memory blocks.