Memory Controller Voltage Detection for Reduced Wake-Up Latency
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Solution Overview
Problem
Recovery from power-saving modes in storage systems is time-consuming due to the need to re-initialize NAND and reload firmware images and data, leading to increased wake-up latency and user experience deterioration.
Innovation Solution
A voltage drop detection circuit is implemented in the memory controller to monitor power supply voltage during sleep states, allowing for a reduced or full initialization procedure based on whether power remained above a threshold, thereby optimizing the recovery process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full initialization procedure is performed to recover from reduced power state, then reliability of data integrity is improved, but wake-up latency increases
Solution Approach 1:
The system performs preliminary actions by monitoring power supply voltage during the reduced power state and preserving critical data in the buffer memory before entering sleep mode. This allows the buffer to retain data without requiring a full initialization procedure upon wake-up, thus reducing wake-up latency while maintaining data integrity through the voltage monitoring mechanism that ensures safe transition states.
Solution Approach 2:
The invention applies local quality by implementing selective initialization rather than a complete system re-initialization. The voltage drop detection circuit and buffer memory work together to preserve specific data structures and metadata that are critical for recovery, while only initializing the minimal necessary components. This localized approach to data preservation and selective initialization reduces the overall recovery time while maintaining essential data integrity.
2Productivity
If power supply voltage is monitored during reduced power state, then recovery process is optimized, but device complexity increases
Solution Approach 1:
The voltage drop detection circuit operates autonomously during the reduced power state, continuously monitoring power supply voltage without requiring external intervention or complex control logic. The circuit self-manages the detection and triggering of wake-up events based on voltage thresholds, eliminating the need for sophisticated power management controllers and reducing overall device complexity while enabling optimized recovery timing.
Solution Approach 2:
The buffer memory serves multiple functions: it acts as a temporary storage during normal operation, preserves data during reduced power state, and enables rapid recovery by maintaining data in an accessible state. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby optimizing recovery speed without proportionally increasing device complexity.
Data Source
AI summary
Devices and techniques are disclosed herein to control recovery of a memory device from a reduced power state. A memory controller can include a detection circuit configured to monitor the power supply voltage to an array of memory cells during the reduced power state. Control circuitry an initialization procedure for recovery of the memory device from the reduced power state, based on the state of the detection circuit.