Memory Controller Voltage Drop Integrity Check
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Solution Overview
Problem
Memory systems face issues with bit-flips due to supply voltage instability, leading to malfunctions and irrecoverable data errors, particularly during operations like reading, writing, or erasing data.
Innovation Solution
A memory system and controller that perform integrity checks and error handling operations when supply voltage drops below certain thresholds, including stopping or correcting firmware execution to prevent malfunctions and data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory system continues operation during voltage drops, then productivity is maintained, but bit-flip errors occur causing malfunctions and data loss
Solution Approach 1:
The system performs integrity check operations on target code before voltage drops cause bit-flip errors. The voltage drop detector identifies upcoming voltage issues, and the memory controller proactively executes integrity checks on firmware code stored in nonvolatile memory, preventing errors before they occur during critical operations
Solution Approach 2:
The system implements a feedback mechanism where the voltage drop detector continuously monitors supply voltage levels and provides real-time information to the memory controller. When voltage instability is detected, the controller responds by executing integrity check operations, creating a closed-loop system that adapts to voltage conditions and maintains data integrity
2Reliability
If integrity check operations are performed frequently, then data integrity is improved, but operation time is increased due to additional check operations
Solution Approach 1:
Instead of continuous integrity checking, the system performs checks periodically based on voltage conditions. The voltage drop detector triggers integrity check operations only when supply voltage becomes unstable, creating a conditional periodic action that balances reliability improvement with minimal time loss during normal operation
Solution Approach 2:
The system changes the operational parameters of integrity checks based on voltage conditions. When voltage is stable, normal operation continues without additional checks. When voltage instability is detected, the system transitions to performing integrity check operations, dynamically adjusting checking frequency based on environmental parameters
3Reliability
If error handling operations are implemented, then reliability is improved by preventing malfunction, but device complexity increases due to additional error handling mechanisms
Solution Approach 1:
The error handling functionality is extracted as a separate, dedicated component within the memory controller. The voltage drop detector and integrity check execution are implemented as distinct functional blocks, allowing error handling to be managed independently from normal operation logic, thus improving reliability without significantly increasing overall system complexity
Solution Approach 2:
The memory controller acts as an intermediary between the voltage drop detector and the firmware execution system. It receives voltage status information, determines when integrity checks are needed, executes appropriate error handling operations, and manages firmware execution accordingly. This intermediary role centralizes complexity in a single component rather than distributing it throughout the system
Data Source
AI summary
Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.