Memory Controller Read Voltage Adjustment for NAND Flash Fail Bit Reduction
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Solution Overview
Problem
Current memory systems face challenges in accurately determining and adjusting read voltages for NAND flash memory to minimize fail bits, leading to inefficiencies in data retrieval, particularly when dealing with memory cells that have been written and then read over time.
Innovation Solution
The memory system employs a memory controller that calculates and adjusts read voltages based on correction amounts, using a combination of standard and offset correction values, and dynamically changes these values based on specific conditions to optimize read processes for blocks of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read voltage is adjusted based on simple initial values, then the control process is simple, but the number of fail bits increases due to inaccurate voltage adjustment
Solution Approach 1:
The patent applies preliminary action by pre-calculating correction amounts and storing them in a correction amount table before actual read operations. The memory controller retrieves and applies these pre-computed correction values to adjust read voltages, eliminating the need for complex real-time calculations during read operations while maintaining high voltage accuracy.
Solution Approach 2:
The patent uses copying by creating a correction amount table that stores pre-computed voltage correction values. Instead of performing complex voltage calculations during each read operation, the system copies and applies the appropriate correction amount from the table based on the specific memory block and word line being accessed, significantly simplifying the control process.
2Reliability
If read voltage is adjusted dynamically for each memory block, then the number of fail bits is reduced, but the processing time increases
Solution Approach 1:
The patent performs preliminary action by pre-calculating and storing correction amounts for different memory blocks and word lines in the correction amount table during manufacturing or initialization. This allows the memory controller to quickly retrieve and apply the appropriate correction values during read operations without performing time-consuming calculations, thus maintaining high data retrieval accuracy while minimizing processing time.
Solution Approach 2:
The patent applies dynamics by enabling the memory controller to dynamically select and apply different correction amounts from the table based on the specific memory block and word line being accessed. This dynamic adaptation allows the system to optimize read voltage for each specific memory region, reducing fail bits while maintaining efficient processing through table lookup rather than complex real-time computation.
3Measurement precision
If correction amounts are calculated and stored for all memory blocks, then read voltage accuracy is improved, but the memory controller's storage requirements and complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the correction amount data into separate entries for different memory blocks and word lines in the correction amount table. This segmented organization allows the memory controller to retrieve only the specific correction values needed for the current read operation rather than managing a single large complex data structure, reducing the perceived complexity while maintaining comprehensive voltage precision across all memory regions.
Solution Approach 2:
The patent uses copying by storing pre-computed correction amounts in a dedicated correction amount table that can be efficiently queried. Instead of implementing complex real-time calculation logic in the memory controller, the system copies the appropriate correction values from the table based on block and word line identifiers, simplifying the controller's functionality while achieving high voltage precision.
Data Source
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AI summary
According to one embodiment, a memory system includes: a non-volatile memory including blocks each including memory cells; and a memory controller configured to execute a first read process of reading data from a first memory cell in a first block by using a first voltage and a second read process of reading data from a second memory cell in the first block by using a second voltage. The memory controller is configured to: maintain, when a first condition is satisfied, a difference between the first and second voltages at a first value, and change both the first and second voltages; and change, when a second condition is satisfied after the first condition has been satisfied, a difference between the first and second voltages from the first value to a second value, and change at least one of the first and second voltages.