Memory Controller Voltage Control for Sensing Accuracy
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Solution Overview
Problem
High-density memory devices face challenges in accurate data sensing due to parasitic and cross-coupling capacitances, which cause variations in bit line bias, leading to threshold voltage shifts and inaccurate readings in neighboring memory cells during program verify operations.
Innovation Solution
The memory controller employs a two-stage voltage approach, pre-charging the capacitance unit with a first voltage and maintaining a second, lower voltage during sensing to limit bit line bias variations, ensuring most sensing current is provided as cell current and reducing channel current, thus preventing threshold voltage shifts in neighboring cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a sense amplifier provides sensing current to a memory cell during a program verify operation, then data sensing is enabled, but parasitic capacitance and cross-coupling capacitance cause channel current to increase, reducing sensing accuracy
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level (e.g., 0.4V) before the sensing operation begins. This pre-charging establishes a stable initial condition that reduces the voltage swing during sensing, thereby minimizing channel current through parasitic and cross-coupling capacitances while ensuring accurate sensing of the memory cell data.
2Productivity
If the bit line bias varies during sensing operation, then sensing current can be provided, but cross-coupling capacitance with adjacent bit lines increases, causing threshold voltage shifts in neighboring cells
Solution Approach 1:
The patent implements equipotentiality by maintaining the bit line at a controlled voltage level (e.g., 0.4V) during the sensing operation. This controlled potential reduces voltage differences between adjacent bit lines, thereby minimizing cross-coupling capacitance effects and preventing threshold voltage shifts in neighboring memory cells while still enabling sensing current flow.
3Quantity of substance
If high-density memory cells are used to increase storage capacity, then more data can be stored, but parasitic capacitance effects become more significant, degrading sensing accuracy
Solution Approach 1:
The patent applies parameter changes by adjusting the bit line voltage to an optimized level (e.g., 0.4V) that is specifically tailored for high-density memory cells. This voltage parameter optimization reduces the impact of parasitic capacitance that becomes more significant in high-density configurations, thereby maintaining sensing accuracy while enabling increased storage capacity through multi-level cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This technique enhances sensing accuracy by maintaining stable bit line bias, preventing cross-coupling capacitance increases and ensuring accurate data access in high-density memory devices like TLC or QLC without shifting threshold voltages, thereby improving sensing noise reduction and maintaining data integrity.
Implementation Method 1
the metal bit line has a parasitic capacitance, and a cross-coupling capacitance due to a coupling effect with one or more adjacent metal bit lines (together, referred to as 'capacitance unit' of the metal bit line)
Data Source
AI summary
A memory device comprises a memory cell array, a plurality of sense amplifiers and a memory controller for controlling the plurality of sense amplifiers. The memory cell array includes a plurality of bit lines, where a bit line is coupled to a plurality of memory cells. A sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line. The memory controller performs operations comprising: during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, where the second voltage is a non-zero voltage that is lower than the first voltage.