Memory Controller Voltage Adjustment for Shared Block Stability
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Solution Overview
Problem
Existing memory devices face instability in operation due to variations in erase and program speeds caused by the state of shared memory blocks, leading to deviations in performance and stability.
Innovation Solution
A memory controller that adjusts the activation voltage level of the block word line based on the state of shared memory blocks, ensuring consistent operation by controlling the path switches connected to selected and shared memory blocks through a block state storage and command controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a shared memory block is connected to multiple global word lines through path switches, then memory access flexibility is improved, but operation stability deteriorates due to variations in erase and program speeds caused by shared block state
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the activation voltage level of the block word line based on the state of the shared memory block. When the shared block is in a first state (e.g., erased), a first activation voltage is applied; when in a second state (e.g., programmed), a second activation voltage is applied. This voltage parameter adjustment compensates for the different erase and program speeds of shared blocks, ensuring stable and consistent memory operations across all blocks regardless of their state.
2Device complexity
If path switches are used to connect memory blocks to global word lines, then memory device complexity is reduced through shared connections, but performance consistency worsens due to state-dependent speed variations in shared blocks
Solution Approach 1:
The patent resolves the performance consistency issue by changing the voltage parameter of the block word line based on the shared block's state. The command controller determines the appropriate activation voltage level (first or second voltage level) corresponding to the shared block's state and applies it to ensure consistent erase and program speeds across all memory blocks, maintaining productivity while preserving the simplified shared connection structure.
3Ease of operation
If a fixed activation voltage level is used for all memory blocks, then control simplicity is maintained, but operational reliability decreases due to speed deviations caused by shared block states
Solution Approach 1:
The patent transitions from a static, fixed voltage approach to a dynamic voltage adjustment mechanism. The command controller continuously monitors the state of shared memory blocks and dynamically adjusts the activation voltage level of the block word line accordingly. This dynamic adaptation maintains operational reliability by compensating for state-dependent speed variations while keeping the control mechanism relatively simple through automated state-based voltage selection.
Data Source
AI summary
The memory controller controls a memory device. The controller is configured to determine to perform a target operation on a first memory block and determine an activation voltage level transferred to a block word line based on block state information of a second memory block.